Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3822951 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 18109093 1 T22 150 T23 169 T24 441287



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 8519565 1 T22 40 T23 153 T24 188210
values[0x0] 6570668 1 T22 58 T23 38 T24 161069
values[0x1] 6841811 1 T22 73 T23 44 T24 171145



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2908297 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 19023747 1 T22 152 T23 180 T24 462130



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 80829 1 T24 2014 T27 10 T28 1
valid_sources[0x01] 76217 1 T24 2067 T27 13 T28 4
valid_sources[0x02] 79243 1 T22 2 T24 2055 T27 5
valid_sources[0x03] 83829 1 T22 3 T24 1915 T27 5
valid_sources[0x04] 78552 1 T24 1990 T27 12 T1 662
valid_sources[0x05] 86985 1 T24 1964 T27 14 T1 571
valid_sources[0x06] 83767 1 T22 2 T24 2049 T27 10
valid_sources[0x07] 79530 1 T24 2057 T27 6 T28 3
valid_sources[0x08] 212378 1 T24 2022 T27 11 T1 654
valid_sources[0x09] 87612 1 T22 2 T24 1976 T27 15
valid_sources[0x0a] 152748 1 T22 1 T24 2173 T25 76028
valid_sources[0x0b] 78326 1 T24 2014 T27 10 T28 1
valid_sources[0x0c] 88222 1 T22 1 T24 2121 T27 13
valid_sources[0x0d] 77976 1 T22 1 T24 1938 T27 13
valid_sources[0x0e] 83632 1 T24 2081 T27 11 T1 691
valid_sources[0x0f] 83924 1 T24 1997 T27 15 T1 637
valid_sources[0x10] 81537 1 T22 1 T24 1973 T26 2
valid_sources[0x11] 71777 1 T22 1 T24 2040 T27 4
valid_sources[0x12] 78778 1 T22 1 T24 2115 T27 13
valid_sources[0x13] 78117 1 T22 1 T24 2075 T27 6
valid_sources[0x14] 172093 1 T24 1976 T27 12 T1 621
valid_sources[0x15] 84042 1 T22 2 T24 2013 T26 6
valid_sources[0x16] 72800 1 T24 1965 T27 11 T28 1
valid_sources[0x17] 74226 1 T22 2 T24 2023 T27 15
valid_sources[0x18] 82443 1 T22 4 T24 2036 T27 19
valid_sources[0x19] 72854 1 T24 2033 T27 13 T1 594
valid_sources[0x1a] 83515 1 T22 2 T24 1996 T27 11
valid_sources[0x1b] 71512 1 T22 1 T24 1917 T27 11
valid_sources[0x1c] 133672 1 T22 3 T24 1960 T26 4
valid_sources[0x1d] 80708 1 T24 2063 T27 14 T28 1
valid_sources[0x1e] 84095 1 T24 2177 T27 10 T1 582
valid_sources[0x1f] 69222 1 T24 2056 T27 11 T28 1
valid_sources[0x20] 71655 1 T24 2031 T27 10 T28 2
valid_sources[0x21] 76295 1 T22 1 T24 1967 T27 14
valid_sources[0x22] 86054 1 T22 1 T24 2052 T27 8
valid_sources[0x23] 85185 1 T24 2058 T27 3 T28 5
valid_sources[0x24] 82368 1 T24 2065 T27 6 T1 611
valid_sources[0x25] 89193 1 T22 2 T24 1892 T27 9
valid_sources[0x26] 85073 1 T24 2013 T27 14 T1 612
valid_sources[0x27] 74492 1 T22 1 T24 2104 T27 20
valid_sources[0x28] 78579 1 T24 2061 T27 16 T1 604
valid_sources[0x29] 80339 1 T22 1 T24 2025 T27 3
valid_sources[0x2a] 73275 1 T24 2049 T27 9 T1 677
valid_sources[0x2b] 81037 1 T24 2099 T26 12 T27 5
valid_sources[0x2c] 76606 1 T22 1 T24 1984 T27 4
valid_sources[0x2d] 80709 1 T24 1989 T27 14 T1 643
valid_sources[0x2e] 82328 1 T24 2117 T27 13 T1 653
valid_sources[0x2f] 78779 1 T24 1995 T27 6 T28 1
valid_sources[0x30] 73397 1 T24 1959 T26 19 T27 9
valid_sources[0x31] 132927 1 T24 1965 T27 10 T1 576
valid_sources[0x32] 76740 1 T24 1973 T27 13 T1 587
valid_sources[0x33] 78802 1 T24 1991 T27 21 T1 699
valid_sources[0x34] 82100 1 T22 1 T24 2059 T27 7
valid_sources[0x35] 75612 1 T24 2010 T27 5 T1 583
valid_sources[0x36] 83812 1 T24 2078 T27 9 T28 2
valid_sources[0x37] 181468 1 T24 2047 T27 7 T1 620
valid_sources[0x38] 92924 1 T24 2060 T27 6 T1 621
valid_sources[0x39] 83908 1 T24 2035 T27 11 T1 620
valid_sources[0x3a] 84187 1 T22 1 T24 2081 T27 7
valid_sources[0x3b] 85192 1 T22 1 T24 1985 T27 8
valid_sources[0x3c] 75488 1 T24 2050 T27 7 T28 5
valid_sources[0x3d] 77951 1 T24 1975 T27 16 T1 627
valid_sources[0x3e] 86394 1 T22 1 T24 2068 T27 14
valid_sources[0x3f] 73837 1 T24 2111 T27 4 T1 624
valid_sources[0x40] 344453 1 T24 2011 T27 18 T1 662
valid_sources[0x41] 79583 1 T22 1 T24 1950 T27 11
valid_sources[0x42] 81461 1 T24 2057 T27 8 T28 1
valid_sources[0x43] 73473 1 T22 2 T24 2109 T27 16
valid_sources[0x44] 87493 1 T22 2 T24 2028 T27 12
valid_sources[0x45] 75323 1 T22 1 T24 1935 T27 16
valid_sources[0x46] 82670 1 T24 2079 T27 11 T1 650
valid_sources[0x47] 86945 1 T22 2 T24 2020 T27 11
valid_sources[0x48] 72118 1 T24 1995 T27 13 T28 2
valid_sources[0x49] 82434 1 T22 1 T24 2008 T26 4
valid_sources[0x4a] 77869 1 T24 2096 T27 9 T28 4
valid_sources[0x4b] 75904 1 T24 2091 T27 18 T28 2
valid_sources[0x4c] 75247 1 T22 1 T24 2045 T27 12
valid_sources[0x4d] 79862 1 T22 4 T24 2076 T27 21
valid_sources[0x4e] 75802 1 T24 2053 T27 9 T1 617
valid_sources[0x4f] 83822 1 T22 1 T24 2015 T26 4
valid_sources[0x50] 81169 1 T24 2044 T27 11 T28 4
valid_sources[0x51] 85479 1 T24 1972 T27 7 T1 623
valid_sources[0x52] 82211 1 T22 1 T24 2004 T27 7
valid_sources[0x53] 75510 1 T22 1 T24 2103 T27 8
valid_sources[0x54] 76671 1 T24 2008 T27 10 T1 657
valid_sources[0x55] 76158 1 T22 1 T24 2011 T27 12
valid_sources[0x56] 82699 1 T22 1 T24 1981 T27 8
valid_sources[0x57] 80937 1 T22 1 T24 1939 T26 7
valid_sources[0x58] 82592 1 T22 1 T24 1964 T27 9
valid_sources[0x59] 88529 1 T24 1931 T27 11 T28 1
valid_sources[0x5a] 75586 1 T24 2076 T26 1 T27 11
valid_sources[0x5b] 74320 1 T22 2 T24 2019 T27 15
valid_sources[0x5c] 75794 1 T22 1 T24 2014 T27 12
valid_sources[0x5d] 84119 1 T24 2127 T27 12 T28 1
valid_sources[0x5e] 83799 1 T22 2 T24 2021 T27 7
valid_sources[0x5f] 84072 1 T24 1937 T27 18 T1 559
valid_sources[0x60] 81305 1 T24 1977 T27 12 T28 3
valid_sources[0x61] 75075 1 T24 2053 T26 15 T27 8
valid_sources[0x62] 80409 1 T22 1 T24 2046 T27 10
valid_sources[0x63] 79410 1 T22 2 T24 2100 T26 1
valid_sources[0x64] 82484 1 T24 2046 T27 5 T1 634
valid_sources[0x65] 75569 1 T24 2094 T27 16 T1 620
valid_sources[0x66] 86368 1 T22 2 T24 1943 T27 11
valid_sources[0x67] 79768 1 T24 1954 T26 20 T27 10
valid_sources[0x68] 85067 1 T22 1 T24 2091 T27 6
valid_sources[0x69] 82109 1 T22 1 T24 2073 T27 8
valid_sources[0x6a] 78043 1 T22 2 T24 2037 T27 8
valid_sources[0x6b] 82032 1 T22 1 T24 1967 T26 2
valid_sources[0x6c] 72596 1 T24 2019 T27 12 T28 2
valid_sources[0x6d] 76918 1 T22 2 T24 1980 T27 16
valid_sources[0x6e] 75368 1 T24 2106 T27 4 T1 573
valid_sources[0x6f] 83058 1 T22 1 T24 2071 T27 7
valid_sources[0x70] 75953 1 T24 2129 T26 8 T27 14
valid_sources[0x71] 71886 1 T22 1 T24 1925 T27 6
valid_sources[0x72] 81982 1 T24 1980 T27 14 T28 1
valid_sources[0x73] 75675 1 T22 1 T24 2183 T27 11
valid_sources[0x74] 80918 1 T24 1992 T27 11 T1 610
valid_sources[0x75] 82896 1 T22 1 T24 2005 T26 2
valid_sources[0x76] 83266 1 T24 2041 T27 14 T1 592
valid_sources[0x77] 76567 1 T22 1 T24 1982 T27 5
valid_sources[0x78] 120579 1 T24 2058 T27 3 T28 1
valid_sources[0x79] 85423 1 T24 2040 T27 13 T28 1
valid_sources[0x7a] 179952 1 T22 2 T24 2056 T27 16
valid_sources[0x7b] 83955 1 T24 2052 T27 14 T1 647
valid_sources[0x7c] 256484 1 T22 1 T24 1911 T27 10
valid_sources[0x7d] 77701 1 T24 1995 T27 18 T1 573
valid_sources[0x7e] 80779 1 T24 2054 T27 12 T28 1
valid_sources[0x7f] 72400 1 T24 2070 T26 6 T27 10
valid_sources[0x80] 85476 1 T22 1 T24 2063 T27 7



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 5021952 1 T22 19 T23 87 T24 120202
values[0x0] all_enables biggest_size 6543421 1 T22 58 T23 38 T24 160101
values[0x1] all_enables biggest_size 6543720 1 T22 73 T23 44 T24 160984

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%