Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	207385072	0	0	0
ctrl_en_input_filter_rd_A	207385072	46231	0	0
intr_ctrl_en_falling_rd_A	207385072	47209	0	0
intr_ctrl_en_lvlhigh_rd_A	207385072	47764	0	0
intr_ctrl_en_lvllow_rd_A	207385072	46131	0	0
intr_ctrl_en_rising_rd_A	207385072	46469	0	0
intr_enable_rd_A	207385072	46382	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	46231	0	0
T1	180771	4594	0	0
T2	24962	121	0	0
T3	0	352	0	0
T4	0	125	0	0
T5	0	2	0	0
T6	0	250	0	0
T7	0	2746	0	0
T8	0	190	0	0
T9	0	3	0	0
T10	0	68	0	0
T11	3293	0	0	0
T12	8679	0	0	0
T13	4524	0	0	0
T14	18271	0	0	0
T15	382195	0	0	0
T16	1478	0	0	0
T17	104608	0	0	0
T18	4458	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	47209	0	0
T1	180771	4613	0	0
T2	24962	118	0	0
T3	0	370	0	0
T4	0	122	0	0
T6	0	276	0	0
T7	0	2721	0	0
T8	0	204	0	0
T9	0	7	0	0
T10	0	45	0	0
T11	3293	0	0	0
T12	8679	0	0	0
T13	4524	0	0	0
T14	18271	0	0	0
T15	382195	0	0	0
T16	1478	0	0	0
T17	104608	0	0	0
T18	4458	0	0	0
T19	0	1	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	47764	0	0
T1	180771	4524	0	0
T2	24962	97	0	0
T3	0	295	0	0
T4	0	220	0	0
T6	0	256	0	0
T7	0	2987	0	0
T8	0	146	0	0
T10	0	29	0	0
T11	3293	0	0	0
T12	8679	0	0	0
T13	4524	0	0	0
T14	18271	0	0	0
T15	382195	0	0	0
T16	1478	0	0	0
T17	104608	0	0	0
T18	4458	0	0	0
T20	0	143	0	0
T21	0	3519	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	46131	0	0
T1	180771	4561	0	0
T2	24962	96	0	0
T3	0	248	0	0
T4	0	144	0	0
T6	0	246	0	0
T7	0	2632	0	0
T8	0	214	0	0
T9	0	3	0	0
T10	0	62	0	0
T11	3293	0	0	0
T12	8679	0	0	0
T13	4524	0	0	0
T14	18271	0	0	0
T15	382195	0	0	0
T16	1478	0	0	0
T17	104608	0	0	0
T18	4458	0	0	0
T20	0	174	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	46469	0	0
T1	180771	4540	0	0
T2	24962	133	0	0
T3	0	330	0	0
T4	0	203	0	0
T5	0	7	0	0
T6	0	218	0	0
T7	0	2818	0	0
T8	0	145	0	0
T9	0	5	0	0
T10	0	29	0	0
T11	3293	0	0	0
T12	8679	0	0	0
T13	4524	0	0	0
T14	18271	0	0	0
T15	382195	0	0	0
T16	1478	0	0	0
T17	104608	0	0	0
T18	4458	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207385072	46382	0	0
T1	180771	4470	0	0
T2	24962	113	0	0
T3	0	278	0	0
T4	0	163	0	0
T6	0	307	0	0
T7	0	2673	0	0
T8	0	186	0	0
T9	0	5	0	0
T10	0	49	0	0
T11	3293	0	0	0
T12	8679	0	0	0
T13	4524	0	0	0
T14	18271	0	0	0
T15	382195	0	0	0
T16	1478	0	0	0
T17	104608	0	0	0
T18	4458	0	0	0
T20	0	94	0	0