Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3156403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13657691

1

T1

3113

T11

59

T12

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6816127	1			T1	1943		T11	48		T12	29
values[0x0]	4918658	1			T1	1019		T11	15		T12	17
values[0x1]	5079309	1			T1	1133		T11	21		T12	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2436243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

14377851

1

T1

3301

T11

64

T12

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58735	1			T13	4		T16	8		T105	3
valid_sources[0x01]	57830	1			T12	1		T16	8		T17	5
valid_sources[0x02]	60594	1			T17	4		T105	3		T106	12
valid_sources[0x03]	60053	1			T17	1		T105	2		T109	1
valid_sources[0x04]	211505	1			T13	1		T16	5		T17	1
valid_sources[0x05]	69332	1			T12	1		T17	1		T18	8
valid_sources[0x06]	63525	1			T12	1		T13	9		T16	2
valid_sources[0x07]	60417	1			T17	1		T18	2		T105	3
valid_sources[0x08]	61478	1			T16	5		T17	4		T18	1
valid_sources[0x09]	61996	1			T12	1		T13	2		T16	4
valid_sources[0x0a]	62171	1			T16	12		T17	4		T105	1
valid_sources[0x0b]	93115	1			T12	1		T16	3		T17	3
valid_sources[0x0c]	70431	1			T16	7		T17	3		T105	5
valid_sources[0x0d]	62747	1			T17	2		T18	2		T105	5
valid_sources[0x0e]	59062	1			T105	4		T109	1		T106	20
valid_sources[0x0f]	69530	1			T13	7		T16	6		T105	3
valid_sources[0x10]	68131	1			T16	5		T21	1		T106	15
valid_sources[0x11]	63409	1			T13	4		T16	4		T17	5
valid_sources[0x12]	57162	1			T13	5		T17	3		T105	3
valid_sources[0x13]	62903	1			T16	1		T17	2		T105	5
valid_sources[0x14]	72528	1			T13	1		T16	9		T17	2
valid_sources[0x15]	58951	1			T17	1		T18	4		T105	3
valid_sources[0x16]	61117	1			T13	8		T16	4		T17	3
valid_sources[0x17]	68897	1			T16	2		T105	1		T109	1
valid_sources[0x18]	60969	1			T16	7		T17	1		T105	4
valid_sources[0x19]	58137	1			T17	2		T18	3		T105	5
valid_sources[0x1a]	60900	1			T16	8		T17	3		T105	2
valid_sources[0x1b]	59893	1			T105	6		T109	1		T106	25
valid_sources[0x1c]	57710	1			T12	2		T16	6		T18	1
valid_sources[0x1d]	65832	1			T13	4		T105	4		T109	1
valid_sources[0x1e]	62622	1			T17	1		T18	4		T105	2
valid_sources[0x1f]	57256	1			T13	2		T16	3		T17	2
valid_sources[0x20]	59797	1			T109	1		T106	21		T23	437
valid_sources[0x21]	65051	1			T12	2		T105	1		T106	29
valid_sources[0x22]	61096	1			T16	1		T17	7		T105	4
valid_sources[0x23]	65036	1			T13	14		T16	4		T105	2
valid_sources[0x24]	62114	1			T16	1		T17	5		T18	1
valid_sources[0x25]	222659	1			T13	2		T16	8		T105	8
valid_sources[0x26]	60137	1			T13	2		T16	4		T105	4
valid_sources[0x27]	62814	1			T16	1		T17	2		T18	6
valid_sources[0x28]	65623	1			T12	1		T16	2		T17	1
valid_sources[0x29]	61499	1			T13	4		T16	4		T105	5
valid_sources[0x2a]	55937	1			T13	7		T16	5		T18	5
valid_sources[0x2b]	60000	1			T16	6		T105	5		T21	13
valid_sources[0x2c]	59220	1			T16	12		T18	1		T105	2
valid_sources[0x2d]	59177	1			T16	8		T105	2		T109	1
valid_sources[0x2e]	67724	1			T12	1		T16	2		T17	1
valid_sources[0x2f]	59524	1			T16	2		T17	3		T109	2
valid_sources[0x30]	61163	1			T13	2		T16	11		T18	3
valid_sources[0x31]	61169	1			T13	4		T16	4		T17	2
valid_sources[0x32]	58948	1			T17	2		T109	3		T106	18
valid_sources[0x33]	62509	1			T16	5		T105	3		T109	1
valid_sources[0x34]	63046	1			T13	1		T16	4		T17	4
valid_sources[0x35]	57230	1			T17	5		T105	1		T106	15
valid_sources[0x36]	63650	1			T13	5		T16	5		T105	3
valid_sources[0x37]	67336	1			T13	4		T16	2		T17	5
valid_sources[0x38]	60166	1			T16	6		T18	1		T21	6
valid_sources[0x39]	61838	1			T17	7		T105	3		T109	2
valid_sources[0x3a]	63270	1			T13	2		T16	6		T105	1
valid_sources[0x3b]	58710	1			T16	2		T17	1		T105	1
valid_sources[0x3c]	59024	1			T12	2		T16	4		T105	1
valid_sources[0x3d]	55737	1			T16	11		T105	2		T21	20
valid_sources[0x3e]	55136	1			T13	3		T16	5		T17	1
valid_sources[0x3f]	60836	1			T16	3		T18	1		T105	2
valid_sources[0x40]	60729	1			T13	17		T16	2		T17	1
valid_sources[0x41]	56561	1			T12	1		T16	2		T105	3
valid_sources[0x42]	59020	1			T16	9		T17	1		T105	2
valid_sources[0x43]	61012	1			T11	84		T16	4		T106	11
valid_sources[0x44]	65860	1			T13	5		T16	1		T17	1
valid_sources[0x45]	58964	1			T13	8		T16	2		T105	1
valid_sources[0x46]	63198	1			T13	3		T109	1		T106	22
valid_sources[0x47]	56358	1			T15	25		T16	7		T17	4
valid_sources[0x48]	57826	1			T16	4		T17	1		T105	1
valid_sources[0x49]	61230	1			T16	1		T17	1		T105	3
valid_sources[0x4a]	62286	1			T18	1		T105	1		T109	2
valid_sources[0x4b]	107470	1			T17	2		T105	3		T109	4
valid_sources[0x4c]	58774	1			T18	3		T105	2		T109	4
valid_sources[0x4d]	60371	1			T13	5		T16	5		T105	4
valid_sources[0x4e]	72135	1			T13	1		T16	10		T18	5
valid_sources[0x4f]	61018	1			T13	9		T16	4		T17	2
valid_sources[0x50]	67908	1			T16	2		T17	2		T18	5
valid_sources[0x51]	57014	1			T13	1		T16	2		T17	1
valid_sources[0x52]	59268	1			T16	13		T17	3		T105	1
valid_sources[0x53]	62210	1			T12	1		T17	2		T18	2
valid_sources[0x54]	63981	1			T13	1		T16	6		T17	2
valid_sources[0x55]	67904	1			T12	1		T13	2		T16	3
valid_sources[0x56]	57983	1			T16	5		T105	1		T21	5
valid_sources[0x57]	55135	1			T16	1		T18	3		T105	1
valid_sources[0x58]	64617	1			T13	1		T16	4		T105	4
valid_sources[0x59]	60907	1			T17	1		T105	4		T106	12
valid_sources[0x5a]	57825	1			T17	2		T18	1		T105	7
valid_sources[0x5b]	61225	1			T13	17		T16	1		T17	4
valid_sources[0x5c]	56333	1			T16	7		T17	2		T105	3
valid_sources[0x5d]	60259	1			T12	2		T13	3		T16	5
valid_sources[0x5e]	58002	1			T16	1		T105	4		T109	1
valid_sources[0x5f]	59513	1			T12	3		T18	3		T105	6
valid_sources[0x60]	60520	1			T16	3		T105	3		T106	15
valid_sources[0x61]	59215	1			T13	2		T16	4		T17	1
valid_sources[0x62]	55174	1			T16	2		T17	1		T106	18
valid_sources[0x63]	95315	1			T13	2		T16	5		T17	1
valid_sources[0x64]	67631	1			T13	6		T17	1		T105	6
valid_sources[0x65]	58787	1			T17	3		T18	1		T105	3
valid_sources[0x66]	61360	1			T13	13		T16	6		T17	3
valid_sources[0x67]	59656	1			T13	4		T16	1		T105	5
valid_sources[0x68]	57736	1			T13	3		T16	4		T109	4
valid_sources[0x69]	58273	1			T16	9		T17	1		T18	1
valid_sources[0x6a]	61151	1			T13	1		T16	4		T17	1
valid_sources[0x6b]	64345	1			T16	4		T17	4		T18	4
valid_sources[0x6c]	62751	1			T13	7		T16	2		T17	1
valid_sources[0x6d]	60079	1			T13	6		T16	3		T105	3
valid_sources[0x6e]	64019	1			T16	2		T17	1		T18	4
valid_sources[0x6f]	61915	1			T16	1		T17	2		T105	2
valid_sources[0x70]	59264	1			T12	1		T13	1		T16	4
valid_sources[0x71]	64650	1			T13	7		T16	4		T17	1
valid_sources[0x72]	65635	1			T16	3		T17	1		T18	1
valid_sources[0x73]	55520	1			T16	6		T105	1		T109	4
valid_sources[0x74]	57515	1			T13	9		T16	10		T17	4
valid_sources[0x75]	65049	1			T16	1		T18	4		T105	3
valid_sources[0x76]	58257	1			T13	11		T105	2		T106	11
valid_sources[0x77]	57463	1			T18	1		T105	2		T109	4
valid_sources[0x78]	63739	1			T16	8		T17	1		T18	7
valid_sources[0x79]	56982	1			T16	2		T18	7		T105	5
valid_sources[0x7a]	65739	1			T12	2		T18	6		T105	1
valid_sources[0x7b]	63879	1			T12	1		T17	3		T105	2
valid_sources[0x7c]	62673	1			T16	11		T17	1		T18	3
valid_sources[0x7d]	59267	1			T16	6		T17	1		T105	3
valid_sources[0x7e]	63512	1			T18	2		T105	2		T109	2
valid_sources[0x7f]	61826	1			T17	3		T18	3		T105	6
valid_sources[0x80]	62216	1			T105	1		T109	2		T106	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3847868

1

T1

961

T11

23

T12

17

values[0x0]

all_enables

biggest_size

4902935

1

T1

1019

T11

15

T12

17

values[0x1]

all_enables

biggest_size

4906888

1

T1

1133

T11

21

T12

17