Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	135477077	0	0	0
ctrl_en_input_filter_rd_A	135477077	95015	0	0
intr_ctrl_en_falling_rd_A	135477077	96902	0	0
intr_ctrl_en_lvlhigh_rd_A	135477077	94211	0	0
intr_ctrl_en_lvllow_rd_A	135477077	96652	0	0
intr_ctrl_en_rising_rd_A	135477077	95214	0	0
intr_enable_rd_A	135477077	93733	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	95015	0	0
T1	44811	257	0	0
T2	0	1353	0	0
T3	0	6754	0	0
T4	0	8756	0	0
T5	0	3169	0	0
T6	0	3012	0	0
T7	0	4207	0	0
T8	0	277	0	0
T9	0	2610	0	0
T10	0	4012	0	0
T11	1557	0	0	0
T12	1232	0	0	0
T13	2004	0	0	0
T14	5967	0	0	0
T15	1396	0	0	0
T16	4176	0	0	0
T17	3563	0	0	0
T18	3873	0	0	0
T19	322980	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	96902	0	0
T1	44811	307	0	0
T2	0	1320	0	0
T3	0	6604	0	0
T4	0	8480	0	0
T5	0	3088	0	0
T6	0	3083	0	0
T7	0	4180	0	0
T8	0	215	0	0
T9	0	2696	0	0
T11	1557	0	0	0
T12	1232	0	0	0
T13	2004	0	0	0
T14	5967	0	0	0
T15	1396	0	0	0
T16	4176	0	0	0
T17	3563	0	0	0
T18	3873	0	0	0
T19	322980	0	0	0
T20	0	7	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	94211	0	0
T1	44811	339	0	0
T2	0	1286	0	0
T3	0	6742	0	0
T4	0	8513	0	0
T5	0	2974	0	0
T6	0	2950	0	0
T7	0	4637	0	0
T8	0	342	0	0
T9	0	2586	0	0
T10	0	4233	0	0
T11	1557	0	0	0
T12	1232	0	0	0
T13	2004	0	0	0
T14	5967	0	0	0
T15	1396	0	0	0
T16	4176	0	0	0
T17	3563	0	0	0
T18	3873	0	0	0
T19	322980	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	96652	0	0
T1	44811	276	0	0
T2	0	1372	0	0
T3	0	6915	0	0
T4	0	8182	0	0
T5	0	3399	0	0
T6	0	2795	0	0
T7	0	4383	0	0
T8	0	270	0	0
T9	0	3020	0	0
T10	0	3943	0	0
T11	1557	0	0	0
T12	1232	0	0	0
T13	2004	0	0	0
T14	5967	0	0	0
T15	1396	0	0	0
T16	4176	0	0	0
T17	3563	0	0	0
T18	3873	0	0	0
T19	322980	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	95214	0	0
T1	44811	265	0	0
T2	0	1345	0	0
T3	0	6790	0	0
T4	0	8308	0	0
T5	0	3271	0	0
T6	0	3084	0	0
T7	0	4387	0	0
T8	0	274	0	0
T9	0	2887	0	0
T10	0	3943	0	0
T11	1557	0	0	0
T12	1232	0	0	0
T13	2004	0	0	0
T14	5967	0	0	0
T15	1396	0	0	0
T16	4176	0	0	0
T17	3563	0	0	0
T18	3873	0	0	0
T19	322980	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135477077	93733	0	0
T1	44811	305	0	0
T2	0	1337	0	0
T3	0	6444	0	0
T4	0	8030	0	0
T5	0	3197	0	0
T6	0	2966	0	0
T7	0	4172	0	0
T8	0	296	0	0
T9	0	2667	0	0
T11	1557	0	0	0
T12	1232	0	0	0
T13	2004	0	0	0
T14	5967	0	0	0
T15	1396	0	0	0
T16	4176	0	0	0
T17	3563	0	0	0
T18	3873	0	0	0
T19	322980	0	0	0
T20	0	2	0	0