Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3833774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17413466

1

T26

153

T27

2196

T28

311

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8425717	1			T26	12		T27	1707		T28	193
values[0x0]	6296152	1			T26	67		T27	676		T28	100
values[0x1]	6525371	1			T26	79		T27	654		T28	112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2939523	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18307717

1

T26

154

T27

2363

T28

328

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	161945	1			T27	9		T32	2		T34	43
valid_sources[0x01]	77106	1			T27	11		T32	1		T35	19
valid_sources[0x02]	77605	1			T27	11		T28	1		T32	3
valid_sources[0x03]	85578	1			T27	5		T28	7		T34	7
valid_sources[0x04]	71708	1			T27	12		T28	3		T32	1
valid_sources[0x05]	82398	1			T27	14		T28	1		T32	4
valid_sources[0x06]	76776	1			T27	17		T32	5		T35	7
valid_sources[0x07]	82448	1			T27	8		T28	1		T35	11
valid_sources[0x08]	74776	1			T27	11		T28	1		T32	4
valid_sources[0x09]	79874	1			T27	4		T32	2		T35	20
valid_sources[0x0a]	78756	1			T27	10		T28	1		T35	31
valid_sources[0x0b]	78439	1			T27	17		T28	2		T32	2
valid_sources[0x0c]	81490	1			T27	7		T28	3		T32	2
valid_sources[0x0d]	80264	1			T27	2		T32	2		T35	17
valid_sources[0x0e]	83552	1			T27	10		T28	4		T32	2
valid_sources[0x0f]	69873	1			T27	2		T28	1		T32	4
valid_sources[0x10]	78309	1			T27	18		T28	2		T32	3
valid_sources[0x11]	79425	1			T27	22		T28	1		T32	5
valid_sources[0x12]	77806	1			T27	4		T28	2		T35	20
valid_sources[0x13]	82314	1			T27	8		T28	3		T32	1
valid_sources[0x14]	89737	1			T27	2		T28	5		T32	8
valid_sources[0x15]	79573	1			T27	11		T32	5		T35	18
valid_sources[0x16]	80405	1			T27	16		T32	5		T35	16
valid_sources[0x17]	83104	1			T27	18		T28	2		T32	2
valid_sources[0x18]	79377	1			T27	8		T28	3		T32	5
valid_sources[0x19]	78755	1			T27	5		T32	2		T34	1
valid_sources[0x1a]	82798	1			T27	10		T28	3		T35	15
valid_sources[0x1b]	111369	1			T27	27		T28	3		T32	2
valid_sources[0x1c]	73932	1			T27	8		T28	9		T32	4
valid_sources[0x1d]	79089	1			T27	3		T28	2		T32	1
valid_sources[0x1e]	74644	1			T27	5		T28	2		T32	4
valid_sources[0x1f]	75054	1			T27	3		T28	1		T32	1
valid_sources[0x20]	72152	1			T27	22		T32	1		T34	2
valid_sources[0x21]	81355	1			T27	14		T28	1		T34	31
valid_sources[0x22]	86060	1			T27	23		T32	1		T35	22
valid_sources[0x23]	82287	1			T27	2		T28	1		T32	2
valid_sources[0x24]	80324	1			T27	21		T28	1		T32	6
valid_sources[0x25]	79926	1			T27	9		T32	2		T35	28
valid_sources[0x26]	81903	1			T27	8		T28	5		T35	21
valid_sources[0x27]	78741	1			T27	33		T28	1		T32	2
valid_sources[0x28]	75984	1			T27	22		T32	1		T35	31
valid_sources[0x29]	88617	1			T27	11		T28	1		T32	1
valid_sources[0x2a]	83374	1			T27	4		T32	4		T35	20
valid_sources[0x2b]	82024	1			T27	12		T28	1		T32	2
valid_sources[0x2c]	70120	1			T27	2		T28	3		T32	2
valid_sources[0x2d]	79714	1			T27	7		T28	1		T35	11
valid_sources[0x2e]	78894	1			T27	9		T28	2		T32	2
valid_sources[0x2f]	80729	1			T27	13		T35	21		T39	7722
valid_sources[0x30]	77515	1			T27	28		T32	1		T34	3
valid_sources[0x31]	79352	1			T27	15		T32	2		T34	3
valid_sources[0x32]	74879	1			T27	29		T28	2		T32	3
valid_sources[0x33]	87862	1			T27	4		T32	1		T35	18
valid_sources[0x34]	78546	1			T27	6		T28	3		T32	1
valid_sources[0x35]	81800	1			T27	24		T32	1		T34	7
valid_sources[0x36]	80926	1			T27	8		T35	18		T36	2
valid_sources[0x37]	82875	1			T27	22		T28	1		T32	1
valid_sources[0x38]	75625	1			T27	8		T28	2		T32	1
valid_sources[0x39]	71110	1			T27	3		T28	1		T32	3
valid_sources[0x3a]	82362	1			T28	8		T35	21		T36	2
valid_sources[0x3b]	73505	1			T27	8		T28	1		T32	1
valid_sources[0x3c]	74520	1			T27	1		T28	1		T32	1
valid_sources[0x3d]	81899	1			T27	16		T28	2		T35	18
valid_sources[0x3e]	79288	1			T27	14		T32	4		T34	44
valid_sources[0x3f]	223675	1			T27	14		T32	1		T34	10
valid_sources[0x40]	79603	1			T27	14		T28	2		T34	15
valid_sources[0x41]	80298	1			T27	4		T32	1		T34	20
valid_sources[0x42]	81983	1			T27	11		T28	2		T32	3
valid_sources[0x43]	83337	1			T27	30		T28	3		T32	4
valid_sources[0x44]	76283	1			T27	11		T28	1		T32	2
valid_sources[0x45]	77001	1			T26	158		T27	12		T28	2
valid_sources[0x46]	75919	1			T27	10		T28	2		T34	3
valid_sources[0x47]	80095	1			T27	6		T35	33		T36	1
valid_sources[0x48]	75704	1			T27	7		T28	4		T32	2
valid_sources[0x49]	84607	1			T27	25		T28	1		T32	2
valid_sources[0x4a]	74691	1			T27	13		T28	2		T32	2
valid_sources[0x4b]	81957	1			T27	13		T35	12		T36	4
valid_sources[0x4c]	76392	1			T27	22		T32	1		T35	18
valid_sources[0x4d]	74376	1			T27	2		T28	4		T34	6
valid_sources[0x4e]	79286	1			T27	31		T28	2		T32	1
valid_sources[0x4f]	82452	1			T27	7		T28	1		T32	3
valid_sources[0x50]	86566	1			T27	8		T28	2		T32	1
valid_sources[0x51]	81034	1			T28	2		T32	1		T34	2
valid_sources[0x52]	73488	1			T27	22		T28	1		T32	3
valid_sources[0x53]	78274	1			T27	15		T28	1		T32	2
valid_sources[0x54]	81177	1			T27	9		T28	1		T35	24
valid_sources[0x55]	199777	1			T27	6		T28	3		T32	2
valid_sources[0x56]	81410	1			T27	10		T29	3		T32	1
valid_sources[0x57]	83414	1			T27	8		T28	2		T35	30
valid_sources[0x58]	85178	1			T27	5		T32	2		T35	16
valid_sources[0x59]	77305	1			T27	14		T32	2		T34	28
valid_sources[0x5a]	77765	1			T27	9		T28	2		T29	2
valid_sources[0x5b]	84239	1			T27	14		T35	22		T36	3
valid_sources[0x5c]	80972	1			T27	16		T32	1		T34	58
valid_sources[0x5d]	88555	1			T27	17		T32	5		T35	26
valid_sources[0x5e]	68886	1			T27	16		T28	1		T35	33
valid_sources[0x5f]	77287	1			T27	16		T34	25		T35	17
valid_sources[0x60]	74722	1			T27	18		T32	2		T34	51
valid_sources[0x61]	70848	1			T27	6		T28	1		T32	5
valid_sources[0x62]	74447	1			T27	11		T28	2		T32	1
valid_sources[0x63]	76450	1			T27	15		T32	7		T35	17
valid_sources[0x64]	84440	1			T27	6		T28	2		T34	38
valid_sources[0x65]	75735	1			T27	14		T35	29		T36	2
valid_sources[0x66]	76257	1			T27	10		T28	1		T32	3
valid_sources[0x67]	78509	1			T27	9		T28	1		T32	4
valid_sources[0x68]	75257	1			T27	11		T32	3		T35	16
valid_sources[0x69]	84332	1			T27	15		T32	3		T35	25
valid_sources[0x6a]	71294	1			T27	5		T28	3		T32	1
valid_sources[0x6b]	76298	1			T27	19		T28	2		T32	2
valid_sources[0x6c]	78271	1			T27	11		T32	1		T34	2
valid_sources[0x6d]	77684	1			T27	10		T28	1		T35	28
valid_sources[0x6e]	79442	1			T27	1		T28	2		T32	4
valid_sources[0x6f]	80619	1			T27	13		T28	4		T35	15
valid_sources[0x70]	77335	1			T27	13		T28	2		T32	1
valid_sources[0x71]	77882	1			T27	22		T28	1		T32	6
valid_sources[0x72]	83701	1			T27	7		T32	1		T34	8
valid_sources[0x73]	75085	1			T27	6		T28	1		T32	1
valid_sources[0x74]	74334	1			T27	10		T28	3		T32	6
valid_sources[0x75]	78636	1			T27	10		T28	5		T32	1
valid_sources[0x76]	84928	1			T27	6		T32	2		T35	26
valid_sources[0x77]	84920	1			T27	3		T28	6		T35	26
valid_sources[0x78]	79722	1			T27	13		T32	5		T35	22
valid_sources[0x79]	79232	1			T27	11		T28	1		T35	24
valid_sources[0x7a]	79011	1			T27	19		T28	2		T35	17
valid_sources[0x7b]	76365	1			T27	24		T28	2		T32	1
valid_sources[0x7c]	84378	1			T27	20		T32	3		T34	38
valid_sources[0x7d]	76255	1			T27	9		T28	2		T32	1
valid_sources[0x7e]	126010	1			T27	11		T28	2		T35	20
valid_sources[0x7f]	76993	1			T27	13		T35	18		T36	6
valid_sources[0x80]	85784	1			T27	17		T28	7		T32	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4868690

1

T26

7

T27

866

T28

99

values[0x0]

all_enables

biggest_size

6272976

1

T26

67

T27

676

T28

100

values[0x1]

all_enables

biggest_size

6271800

1

T26

79

T27

654

T28

112