Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	174708080	0	0	0
ctrl_en_input_filter_rd_A	174708080	85303	0	0
intr_ctrl_en_falling_rd_A	174708080	87841	0	0
intr_ctrl_en_lvlhigh_rd_A	174708080	84807	0	0
intr_ctrl_en_lvllow_rd_A	174708080	88838	0	0
intr_ctrl_en_rising_rd_A	174708080	84859	0	0
intr_enable_rd_A	174708080	84659	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	85303	0	0
T1	428009	1767	0	0
T2	748900	2440	0	0
T3	0	199	0	0
T4	0	2	0	0
T5	0	131	0	0
T6	0	3247	0	0
T7	0	10	0	0
T8	0	51	0	0
T9	0	3078	0	0
T10	0	4389	0	0
T11	7303	0	0	0
T12	11893	0	0	0
T13	2753	0	0	0
T14	3693	0	0	0
T15	2387	0	0	0
T16	338448	0	0	0
T17	116096	0	0	0
T18	5535	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	87841	0	0
T1	428009	1829	0	0
T2	748900	2532	0	0
T3	0	230	0	0
T4	0	2	0	0
T5	0	128	0	0
T6	0	3481	0	0
T7	0	2	0	0
T11	7303	0	0	0
T12	11893	0	0	0
T13	2753	0	0	0
T14	3693	0	0	0
T19	2361	4	0	0
T20	0	1	0	0
T21	0	8	0	0
T22	3137	0	0	0
T23	2120	0	0	0
T24	3491	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	84807	0	0
T1	428009	1881	0	0
T2	748900	2610	0	0
T3	0	236	0	0
T5	0	151	0	0
T6	0	3438	0	0
T7	0	2	0	0
T8	0	48	0	0
T9	0	2796	0	0
T10	0	4257	0	0
T11	7303	0	0	0
T12	11893	0	0	0
T13	2753	0	0	0
T14	3693	0	0	0
T15	2387	0	0	0
T16	338448	0	0	0
T17	116096	0	0	0
T18	5535	0	0	0
T25	0	12	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	88838	0	0
T1	428009	1675	0	0
T2	748900	2707	0	0
T3	0	233	0	0
T4	0	2	0	0
T5	0	140	0	0
T6	0	3093	0	0
T8	0	50	0	0
T9	0	3260	0	0
T11	7303	0	0	0
T12	11893	0	0	0
T13	2753	0	0	0
T14	3693	0	0	0
T15	2387	0	0	0
T16	338448	0	0	0
T17	116096	0	0	0
T18	5535	0	0	0
T21	0	11	0	0
T25	0	6	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	84859	0	0
T1	428009	1670	0	0
T2	748900	2545	0	0
T3	0	184	0	0
T4	0	3	0	0
T5	0	142	0	0
T6	0	3337	0	0
T8	0	34	0	0
T11	7303	0	0	0
T12	11893	0	0	0
T13	2753	0	0	0
T14	3693	0	0	0
T19	2361	5	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	3137	0	0	0
T23	2120	0	0	0
T24	3491	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174708080	84659	0	0
T1	428009	1679	0	0
T2	748900	2492	0	0
T3	0	234	0	0
T4	0	5	0	0
T5	0	173	0	0
T6	0	3126	0	0
T8	0	30	0	0
T11	7303	0	0	0
T12	11893	0	0	0
T13	2753	0	0	0
T14	3693	0	0	0
T15	2387	0	0	0
T16	338448	0	0	0
T17	116096	0	0	0
T18	5535	0	0	0
T20	0	5	0	0
T21	0	9	0	0
T25	0	4	0	0