Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2892868	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12631704

1

T21

248

T22

3030

T23

1434

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6263805	1			T21	138		T22	4604		T23	1719
values[0x0]	4560294	1			T21	94		T22	313		T23	291
values[0x1]	4700473	1			T21	79		T22	382		T23	299

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2234395	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

13290177

1

T21

261

T22

3493

T23

1600

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59375	1			T22	16		T25	2		T29	5
valid_sources[0x01]	61846	1			T22	16		T25	2		T29	1
valid_sources[0x02]	56573	1			T22	21		T29	7		T115	1
valid_sources[0x03]	58563	1			T22	31		T25	2		T29	2
valid_sources[0x04]	56587	1			T22	29		T25	1		T27	1
valid_sources[0x05]	57601	1			T22	10		T25	2		T29	8
valid_sources[0x06]	58941	1			T22	16		T25	3		T27	1
valid_sources[0x07]	56519	1			T22	23		T116	18		T50	1
valid_sources[0x08]	61059	1			T22	24		T30	9		T43	1
valid_sources[0x09]	58466	1			T22	34		T43	3		T115	1
valid_sources[0x0a]	60953	1			T22	41		T25	2		T29	1
valid_sources[0x0b]	56264	1			T22	27		T27	1		T29	8
valid_sources[0x0c]	58918	1			T22	9		T25	1		T43	2
valid_sources[0x0d]	60043	1			T22	28		T25	2		T115	2
valid_sources[0x0e]	112966	1			T22	12		T25	1		T30	1
valid_sources[0x0f]	61726	1			T22	17		T27	2		T29	11
valid_sources[0x10]	57608	1			T22	14		T25	1		T43	1
valid_sources[0x11]	59000	1			T22	24		T27	6		T115	1
valid_sources[0x12]	66300	1			T22	30		T25	2		T27	3
valid_sources[0x13]	56365	1			T22	9		T25	3		T43	1
valid_sources[0x14]	60154	1			T22	30		T25	1		T115	4
valid_sources[0x15]	175076	1			T22	24		T25	1		T115	1
valid_sources[0x16]	60195	1			T22	36		T25	1		T29	8
valid_sources[0x17]	60543	1			T22	23		T29	1		T30	2
valid_sources[0x18]	56448	1			T22	12		T43	1		T115	2
valid_sources[0x19]	57561	1			T22	16		T25	1		T29	6
valid_sources[0x1a]	56089	1			T22	24		T27	2		T29	12
valid_sources[0x1b]	55716	1			T22	9		T29	20		T30	59
valid_sources[0x1c]	59173	1			T22	13		T29	3		T115	1
valid_sources[0x1d]	66678	1			T22	18		T27	4		T29	2
valid_sources[0x1e]	57589	1			T22	25		T25	1		T116	17
valid_sources[0x1f]	56281	1			T22	11		T29	7		T115	3
valid_sources[0x20]	59171	1			T22	11		T25	1		T27	2
valid_sources[0x21]	58227	1			T22	6		T25	3		T115	2
valid_sources[0x22]	56065	1			T22	11		T25	1		T27	2
valid_sources[0x23]	58663	1			T22	14		T25	1		T115	1
valid_sources[0x24]	57882	1			T22	35		T27	2		T29	3
valid_sources[0x25]	61326	1			T22	19		T25	1		T29	3
valid_sources[0x26]	58629	1			T22	18		T27	4		T29	8
valid_sources[0x27]	54906	1			T22	27		T27	1		T29	8
valid_sources[0x28]	64234	1			T22	13		T25	2		T29	1
valid_sources[0x29]	56084	1			T22	12		T25	3		T27	13
valid_sources[0x2a]	63316	1			T22	13		T25	2		T43	4
valid_sources[0x2b]	57673	1			T22	14		T25	2		T30	2
valid_sources[0x2c]	59669	1			T22	21		T30	10		T116	19
valid_sources[0x2d]	59315	1			T22	30		T25	3		T29	12
valid_sources[0x2e]	59037	1			T22	16		T116	18		T50	5
valid_sources[0x2f]	55365	1			T22	32		T25	1		T29	4
valid_sources[0x30]	57018	1			T22	13		T25	1		T27	1
valid_sources[0x31]	57949	1			T22	25		T43	1		T115	2
valid_sources[0x32]	58024	1			T22	34		T29	2		T43	3
valid_sources[0x33]	57942	1			T22	8		T25	1		T115	2
valid_sources[0x34]	58552	1			T22	21		T25	1		T29	6
valid_sources[0x35]	61214	1			T22	9		T29	5		T43	3
valid_sources[0x36]	57049	1			T22	19		T25	1		T27	8
valid_sources[0x37]	55982	1			T22	6		T27	1		T29	5
valid_sources[0x38]	55202	1			T22	7		T25	1		T115	1
valid_sources[0x39]	58745	1			T22	7		T30	1		T43	1
valid_sources[0x3a]	59805	1			T22	15		T25	1		T29	5
valid_sources[0x3b]	60448	1			T22	12		T25	1		T29	4
valid_sources[0x3c]	59326	1			T22	14		T29	3		T43	1
valid_sources[0x3d]	59285	1			T22	18		T27	5		T29	3
valid_sources[0x3e]	57518	1			T22	19		T25	2		T29	1
valid_sources[0x3f]	58285	1			T22	19		T25	3		T29	6
valid_sources[0x40]	58167	1			T22	7		T25	1		T27	1
valid_sources[0x41]	62203	1			T22	20		T27	4		T29	1
valid_sources[0x42]	56343	1			T22	18		T25	2		T43	1
valid_sources[0x43]	57133	1			T22	12		T27	1		T115	1
valid_sources[0x44]	56134	1			T22	16		T29	2		T115	2
valid_sources[0x45]	58743	1			T22	19		T25	1		T29	2
valid_sources[0x46]	61626	1			T22	19		T25	1		T27	9
valid_sources[0x47]	59064	1			T22	22		T29	2		T116	16
valid_sources[0x48]	60073	1			T22	23		T29	6		T116	18
valid_sources[0x49]	56867	1			T22	10		T25	1		T29	3
valid_sources[0x4a]	61148	1			T22	20		T25	5		T116	23
valid_sources[0x4b]	60100	1			T22	11		T29	2		T116	26
valid_sources[0x4c]	56875	1			T22	26		T25	4		T27	2
valid_sources[0x4d]	60354	1			T22	20		T29	11		T115	4
valid_sources[0x4e]	55514	1			T22	21		T27	6		T43	2
valid_sources[0x4f]	57447	1			T22	18		T25	1		T27	10
valid_sources[0x50]	63809	1			T22	21		T25	3		T115	3
valid_sources[0x51]	56985	1			T22	35		T27	5		T115	2
valid_sources[0x52]	57478	1			T22	32		T25	4		T43	8
valid_sources[0x53]	58365	1			T22	18		T43	3		T115	1
valid_sources[0x54]	60155	1			T22	36		T25	4		T27	2
valid_sources[0x55]	62488	1			T21	311		T22	19		T27	1
valid_sources[0x56]	59396	1			T22	31		T25	3		T29	3
valid_sources[0x57]	59575	1			T22	16		T25	1		T27	2
valid_sources[0x58]	61592	1			T22	17		T25	2		T43	1
valid_sources[0x59]	59618	1			T22	19		T25	3		T29	1
valid_sources[0x5a]	55592	1			T22	16		T25	1		T27	1
valid_sources[0x5b]	60061	1			T22	21		T25	1		T27	2
valid_sources[0x5c]	54811	1			T22	27		T29	4		T115	2
valid_sources[0x5d]	57607	1			T22	24		T25	1		T116	18
valid_sources[0x5e]	58629	1			T22	28		T25	1		T115	1
valid_sources[0x5f]	57246	1			T22	25		T29	3		T43	3
valid_sources[0x60]	57719	1			T22	27		T25	2		T29	3
valid_sources[0x61]	56699	1			T22	21		T25	1		T27	4
valid_sources[0x62]	56534	1			T22	15		T27	4		T29	1
valid_sources[0x63]	58053	1			T22	16		T29	6		T115	2
valid_sources[0x64]	62053	1			T22	14		T116	16		T50	1
valid_sources[0x65]	57957	1			T22	14		T115	1		T116	13
valid_sources[0x66]	61049	1			T22	34		T25	1		T43	1
valid_sources[0x67]	59997	1			T22	12		T25	1		T116	17
valid_sources[0x68]	60806	1			T22	36		T115	1		T116	14
valid_sources[0x69]	57985	1			T22	18		T29	3		T43	2
valid_sources[0x6a]	59476	1			T22	22		T27	3		T29	1
valid_sources[0x6b]	56797	1			T22	22		T25	1		T27	1
valid_sources[0x6c]	60237	1			T22	20		T43	3		T115	2
valid_sources[0x6d]	57230	1			T22	28		T25	1		T29	6
valid_sources[0x6e]	57129	1			T22	8		T25	1		T43	1
valid_sources[0x6f]	55932	1			T22	14		T26	181		T29	18
valid_sources[0x70]	55731	1			T22	30		T25	3		T29	1
valid_sources[0x71]	54852	1			T22	30		T43	3		T115	2
valid_sources[0x72]	193809	1			T22	18		T25	2		T27	1
valid_sources[0x73]	60033	1			T22	12		T27	3		T29	12
valid_sources[0x74]	59470	1			T22	16		T29	6		T30	19
valid_sources[0x75]	57675	1			T22	21		T25	2		T29	3
valid_sources[0x76]	58358	1			T22	14		T25	2		T29	1
valid_sources[0x77]	59369	1			T22	21		T27	1		T29	3
valid_sources[0x78]	59207	1			T22	25		T25	1		T29	2
valid_sources[0x79]	58392	1			T22	20		T25	1		T29	1
valid_sources[0x7a]	58448	1			T22	15		T25	2		T43	1
valid_sources[0x7b]	56099	1			T22	25		T25	1		T43	1
valid_sources[0x7c]	58222	1			T22	25		T25	2		T27	3
valid_sources[0x7d]	57583	1			T22	22		T25	2		T27	2
valid_sources[0x7e]	66263	1			T22	23		T23	2309		T25	3
valid_sources[0x7f]	58593	1			T22	11		T25	3		T43	2
valid_sources[0x80]	59654	1			T22	11		T25	1		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3544324

1

T21

75

T22

2335

T23

844

values[0x0]

all_enables

biggest_size

4545663

1

T21

94

T22

313

T23

291

values[0x1]

all_enables

biggest_size

4541717

1

T21

79

T22

382

T23

299