Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	141461112	0	0	0
ctrl_en_input_filter_rd_A	141461112	137850	0	0
intr_ctrl_en_falling_rd_A	141461112	143670	0	0
intr_ctrl_en_lvlhigh_rd_A	141461112	136222	0	0
intr_ctrl_en_lvllow_rd_A	141461112	144691	0	0
intr_ctrl_en_rising_rd_A	141461112	136755	0	0
intr_enable_rd_A	141461112	138826	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	137850	0	0
T1	11990	65	0	0
T2	0	2	0	0
T3	0	8	0	0
T4	0	2804	0	0
T5	0	2183	0	0
T6	0	5	0	0
T7	0	920	0	0
T8	0	400	0	0
T9	0	45	0	0
T10	0	2	0	0
T11	1317	0	0	0
T12	14625	0	0	0
T13	33029	0	0	0
T14	361167	0	0	0
T15	5976	0	0	0
T16	7452	0	0	0
T17	11548	0	0	0
T18	68943	0	0	0
T19	4333	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	143670	0	0
T1	11990	32	0	0
T3	0	6	0	0
T4	0	2909	0	0
T5	0	2166	0	0
T6	0	3	0	0
T7	0	949	0	0
T8	0	371	0	0
T9	0	36	0	0
T10	0	3	0	0
T11	1317	0	0	0
T12	14625	0	0	0
T13	33029	0	0	0
T14	361167	0	0	0
T15	5976	0	0	0
T16	7452	0	0	0
T17	11548	0	0	0
T18	68943	0	0	0
T19	4333	0	0	0
T20	0	3857	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	136222	0	0
T1	11990	57	0	0
T2	0	1	0	0
T3	0	1	0	0
T4	0	2983	0	0
T5	0	2105	0	0
T6	0	1	0	0
T7	0	981	0	0
T8	0	401	0	0
T9	0	62	0	0
T10	0	9	0	0
T11	1317	0	0	0
T12	14625	0	0	0
T13	33029	0	0	0
T14	361167	0	0	0
T15	5976	0	0	0
T16	7452	0	0	0
T17	11548	0	0	0
T18	68943	0	0	0
T19	4333	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	144691	0	0
T1	11990	76	0	0
T2	0	10	0	0
T3	0	5	0	0
T4	0	3006	0	0
T5	0	2138	0	0
T6	0	14	0	0
T7	0	988	0	0
T8	0	353	0	0
T9	0	82	0	0
T11	1317	0	0	0
T12	14625	0	0	0
T13	33029	0	0	0
T14	361167	0	0	0
T15	5976	0	0	0
T16	7452	0	0	0
T17	11548	0	0	0
T18	68943	0	0	0
T19	4333	0	0	0
T20	0	3862	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	136755	0	0
T1	11990	39	0	0
T2	0	1	0	0
T3	0	7	0	0
T4	0	2872	0	0
T5	0	2250	0	0
T6	0	12	0	0
T7	0	984	0	0
T8	0	371	0	0
T9	0	82	0	0
T10	0	5	0	0
T11	1317	0	0	0
T12	14625	0	0	0
T13	33029	0	0	0
T14	361167	0	0	0
T15	5976	0	0	0
T16	7452	0	0	0
T17	11548	0	0	0
T18	68943	0	0	0
T19	4333	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141461112	138826	0	0
T1	11990	29	0	0
T3	0	4	0	0
T4	0	3075	0	0
T5	0	2318	0	0
T6	0	5	0	0
T7	0	1114	0	0
T8	0	396	0	0
T9	0	66	0	0
T10	0	10	0	0
T11	1317	0	0	0
T12	14625	0	0	0
T13	33029	0	0	0
T14	361167	0	0	0
T15	5976	0	0	0
T16	7452	0	0	0
T17	11548	0	0	0
T18	68943	0	0	0
T19	4333	0	0	0
T20	0	3955	0	0