Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3593016	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16255068

1

T29

192

T30

81

T31

281

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7878893	1			T29	122		T30	40		T31	40
values[0x0]	5874296	1			T29	73		T30	32		T31	148
values[0x1]	6094895	1			T29	63		T30	24		T31	112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2755422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17092662

1

T29

204

T30

84

T31

282

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	75185	1			T29	4		T31	1		T32	1
valid_sources[0x01]	72788	1			T31	2		T33	3		T20	1
valid_sources[0x02]	68662	1			T31	4		T33	1		T20	3
valid_sources[0x03]	81765	1			T31	1		T33	3		T20	4
valid_sources[0x04]	80347	1			T29	3		T31	3		T33	2
valid_sources[0x05]	68622	1			T31	1		T32	4		T20	2
valid_sources[0x06]	72202	1			T29	2		T31	3		T20	2
valid_sources[0x07]	73243	1			T31	1		T33	2		T21	2
valid_sources[0x08]	74322	1			T29	3		T31	2		T32	1
valid_sources[0x09]	69601	1			T31	4		T33	1		T21	2
valid_sources[0x0a]	70406	1			T31	3		T33	4		T20	1
valid_sources[0x0b]	71096	1			T31	4		T32	4		T33	2
valid_sources[0x0c]	69997	1			T31	1		T33	3		T20	1
valid_sources[0x0d]	71189	1			T31	1		T33	1		T20	1
valid_sources[0x0e]	67444	1			T21	3		T22	15		T25	2
valid_sources[0x0f]	118842	1			T31	1		T32	4		T33	1
valid_sources[0x10]	69731	1			T20	1		T21	7		T22	9
valid_sources[0x11]	82527	1			T31	1		T32	1		T33	2
valid_sources[0x12]	73945	1			T30	3		T31	2		T33	1
valid_sources[0x13]	68284	1			T31	1		T32	4		T33	1
valid_sources[0x14]	72369	1			T29	2		T31	3		T21	3
valid_sources[0x15]	71721	1			T31	2		T33	3		T20	2
valid_sources[0x16]	75188	1			T29	1		T31	2		T32	2
valid_sources[0x17]	71709	1			T29	1		T31	3		T33	1
valid_sources[0x18]	73201	1			T32	2		T33	2		T20	1
valid_sources[0x19]	72862	1			T31	1		T21	3		T22	11
valid_sources[0x1a]	74817	1			T32	4		T33	3		T20	3
valid_sources[0x1b]	212276	1			T29	1		T33	1		T20	1
valid_sources[0x1c]	67175	1			T30	6		T31	1		T33	1
valid_sources[0x1d]	152583	1			T32	1		T33	2		T21	6
valid_sources[0x1e]	75964	1			T31	1		T20	2		T21	2
valid_sources[0x1f]	80318	1			T32	3		T33	1		T20	1
valid_sources[0x20]	74174	1			T33	2		T20	2		T21	4
valid_sources[0x21]	79395	1			T29	1		T33	2		T20	2
valid_sources[0x22]	71614	1			T29	1		T31	1		T32	2
valid_sources[0x23]	79588	1			T30	1		T31	1		T33	1
valid_sources[0x24]	70350	1			T29	7		T32	6		T33	2
valid_sources[0x25]	71191	1			T29	4		T33	1		T20	2
valid_sources[0x26]	67893	1			T33	2		T20	1		T21	1
valid_sources[0x27]	69124	1			T32	1		T33	1		T21	4
valid_sources[0x28]	70705	1			T29	3		T32	2		T33	3
valid_sources[0x29]	74274	1			T29	5		T31	1		T32	4
valid_sources[0x2a]	71281	1			T31	1		T33	2		T20	1
valid_sources[0x2b]	78465	1			T31	2		T33	2		T20	3
valid_sources[0x2c]	79849	1			T30	8		T33	2		T20	1
valid_sources[0x2d]	74595	1			T29	1		T21	4		T22	9
valid_sources[0x2e]	86923	1			T31	1		T32	7		T20	2
valid_sources[0x2f]	75243	1			T29	2		T30	2		T31	2
valid_sources[0x30]	71438	1			T30	4		T33	2		T20	2
valid_sources[0x31]	74827	1			T31	3		T33	4		T20	1
valid_sources[0x32]	77800	1			T31	1		T33	3		T20	1
valid_sources[0x33]	71663	1			T30	4		T31	1		T20	2
valid_sources[0x34]	72009	1			T32	1		T33	2		T21	3
valid_sources[0x35]	74454	1			T31	1		T33	5		T21	6
valid_sources[0x36]	69244	1			T32	1		T21	3		T22	5
valid_sources[0x37]	74916	1			T29	2		T31	1		T32	1
valid_sources[0x38]	74135	1			T33	3		T21	1		T22	12
valid_sources[0x39]	76485	1			T31	4		T32	5		T33	2
valid_sources[0x3a]	85660	1			T33	1		T20	1		T21	3
valid_sources[0x3b]	71419	1			T29	2		T31	2		T32	1
valid_sources[0x3c]	72098	1			T29	2		T31	1		T32	2
valid_sources[0x3d]	81875	1			T33	3		T21	3		T22	8
valid_sources[0x3e]	67043	1			T29	2		T31	2		T32	2
valid_sources[0x3f]	80756	1			T29	1		T33	1		T20	1
valid_sources[0x40]	76223	1			T29	2		T32	5		T33	5
valid_sources[0x41]	68859	1			T29	2		T30	9		T31	2
valid_sources[0x42]	74437	1			T31	4		T33	1		T20	1
valid_sources[0x43]	101263	1			T29	1		T32	1		T33	4
valid_sources[0x44]	71719	1			T31	1		T32	1		T33	1
valid_sources[0x45]	75201	1			T33	1		T20	2		T21	3
valid_sources[0x46]	79269	1			T29	2		T32	1		T33	2
valid_sources[0x47]	73084	1			T33	1		T20	1		T21	5
valid_sources[0x48]	68792	1			T29	1		T31	2		T33	1
valid_sources[0x49]	100452	1			T31	5		T33	4		T21	1
valid_sources[0x4a]	72323	1			T31	1		T33	3		T20	1
valid_sources[0x4b]	73862	1			T29	3		T31	2		T32	1
valid_sources[0x4c]	75124	1			T31	1		T32	1		T33	6
valid_sources[0x4d]	69737	1			T31	1		T33	3		T20	5
valid_sources[0x4e]	80852	1			T29	3		T32	1		T33	3
valid_sources[0x4f]	67394	1			T32	2		T20	1		T21	1
valid_sources[0x50]	66014	1			T29	1		T31	1		T32	2
valid_sources[0x51]	76948	1			T29	2		T20	2		T21	2
valid_sources[0x52]	72678	1			T29	1		T33	1		T20	1
valid_sources[0x53]	77535	1			T29	5		T31	4		T33	1
valid_sources[0x54]	75785	1			T29	6		T31	2		T32	1
valid_sources[0x55]	72577	1			T29	1		T30	10		T31	1
valid_sources[0x56]	75537	1			T29	1		T31	1		T33	3
valid_sources[0x57]	76957	1			T30	1		T31	3		T33	1
valid_sources[0x58]	71394	1			T31	3		T21	4		T22	11
valid_sources[0x59]	67656	1			T29	1		T30	16		T33	2
valid_sources[0x5a]	74235	1			T29	6		T32	6		T33	2
valid_sources[0x5b]	69459	1			T31	4		T32	1		T33	2
valid_sources[0x5c]	70611	1			T31	2		T33	2		T21	1
valid_sources[0x5d]	70744	1			T30	2		T33	5		T21	1
valid_sources[0x5e]	79634	1			T32	2		T20	2		T21	6
valid_sources[0x5f]	74291	1			T31	2		T33	3		T20	1
valid_sources[0x60]	71254	1			T29	3		T31	1		T32	1
valid_sources[0x61]	72860	1			T29	6		T32	1		T33	3
valid_sources[0x62]	69752	1			T32	6		T21	1		T22	17
valid_sources[0x63]	74097	1			T32	1		T21	3		T22	8
valid_sources[0x64]	69271	1			T32	1		T33	2		T20	4
valid_sources[0x65]	74528	1			T33	1		T20	1		T21	2
valid_sources[0x66]	70690	1			T29	1		T32	1		T33	2
valid_sources[0x67]	82024	1			T29	2		T32	1		T33	1
valid_sources[0x68]	73277	1			T31	2		T33	2		T20	2
valid_sources[0x69]	71171	1			T29	1		T20	1		T21	3
valid_sources[0x6a]	75863	1			T29	2		T31	1		T33	3
valid_sources[0x6b]	74270	1			T31	1		T33	2		T20	1
valid_sources[0x6c]	78325	1			T33	3		T21	4		T22	6
valid_sources[0x6d]	67154	1			T29	3		T31	1		T33	4
valid_sources[0x6e]	82858	1			T31	1		T33	2		T20	3
valid_sources[0x6f]	70623	1			T29	1		T33	1		T20	1
valid_sources[0x70]	185868	1			T32	5		T33	2		T20	3
valid_sources[0x71]	77900	1			T31	1		T33	3		T20	3
valid_sources[0x72]	68714	1			T29	8		T31	1		T32	3
valid_sources[0x73]	73799	1			T32	4		T33	2		T21	3
valid_sources[0x74]	71236	1			T31	2		T33	2		T20	1
valid_sources[0x75]	71670	1			T29	5		T31	3		T33	3
valid_sources[0x76]	78386	1			T29	1		T31	1		T33	3
valid_sources[0x77]	68358	1			T29	2		T33	1		T21	6
valid_sources[0x78]	64786	1			T29	1		T31	4		T33	1
valid_sources[0x79]	72080	1			T29	4		T33	1		T20	4
valid_sources[0x7a]	77121	1			T29	6		T31	2		T33	3
valid_sources[0x7b]	76522	1			T32	5		T33	1		T21	4
valid_sources[0x7c]	75073	1			T31	3		T33	3		T20	1
valid_sources[0x7d]	85969	1			T31	2		T33	2		T20	2
valid_sources[0x7e]	76005	1			T33	3		T20	3		T21	3
valid_sources[0x7f]	72299	1			T31	2		T33	2		T20	1
valid_sources[0x80]	69423	1			T31	3		T33	1		T34	208

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4543668

1

T29

56

T30

25

T31

21

values[0x0]

all_enables

biggest_size

5852459

1

T29

73

T30

32

T31

148

values[0x1]

all_enables

biggest_size

5858941

1

T29

63

T30

24

T31

112