Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	164206080	0	0	0
ctrl_en_input_filter_rd_A	164206080	86141	0	0
intr_ctrl_en_falling_rd_A	164206080	88911	0	0
intr_ctrl_en_lvlhigh_rd_A	164206080	86444	0	0
intr_ctrl_en_lvllow_rd_A	164206080	88142	0	0
intr_ctrl_en_rising_rd_A	164206080	85548	0	0
intr_enable_rd_A	164206080	86629	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	86141	0	0
T1	14649	78	0	0
T2	125710	3081	0	0
T3	4463	4	0	0
T4	0	171	0	0
T5	0	81	0	0
T6	0	4101	0	0
T7	0	5680	0	0
T8	0	160	0	0
T9	0	4079	0	0
T10	0	2272	0	0
T11	4499	0	0	0
T12	5853	0	0	0
T13	22879	0	0	0
T14	10979	0	0	0
T15	2932	0	0	0
T16	107857	0	0	0
T17	10806	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	88911	0	0
T1	14649	87	0	0
T2	125710	3015	0	0
T3	4463	0	0	0
T4	0	151	0	0
T5	0	45	0	0
T6	0	4070	0	0
T7	0	5464	0	0
T8	0	222	0	0
T9	0	3998	0	0
T10	0	2219	0	0
T11	4499	0	0	0
T12	5853	0	0	0
T13	22879	0	0	0
T14	10979	0	0	0
T15	2932	0	0	0
T16	107857	0	0	0
T17	10806	0	0	0
T18	0	17	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	86444	0	0
T1	0	83	0	0
T2	0	3119	0	0
T4	0	124	0	0
T5	0	53	0	0
T6	0	4278	0	0
T7	0	5662	0	0
T8	0	192	0	0
T9	0	4346	0	0
T18	0	2	0	0
T19	4798	5	0	0
T20	3255	0	0	0
T21	6830	0	0	0
T22	35155	0	0	0
T23	3329	0	0	0
T24	6923	0	0	0
T25	3448	0	0	0
T26	5171	0	0	0
T27	833	0	0	0
T28	7163	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	88142	0	0
T1	14649	92	0	0
T2	125710	3233	0	0
T3	4463	16	0	0
T4	0	137	0	0
T5	0	74	0	0
T6	0	4088	0	0
T7	0	5456	0	0
T8	0	175	0	0
T9	0	4186	0	0
T11	4499	0	0	0
T12	5853	0	0	0
T13	22879	0	0	0
T14	10979	0	0	0
T15	2932	0	0	0
T16	107857	0	0	0
T17	10806	0	0	0
T18	0	11	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	85548	0	0
T1	0	111	0	0
T2	0	2935	0	0
T4	0	155	0	0
T5	0	29	0	0
T6	0	3976	0	0
T7	0	5654	0	0
T8	0	236	0	0
T9	0	4166	0	0
T18	0	17	0	0
T19	4798	7	0	0
T20	3255	0	0	0
T21	6830	0	0	0
T22	35155	0	0	0
T23	3329	0	0	0
T24	6923	0	0	0
T25	3448	0	0	0
T26	5171	0	0	0
T27	833	0	0	0
T28	7163	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164206080	86629	0	0
T1	0	109	0	0
T2	0	3116	0	0
T4	0	142	0	0
T5	0	49	0	0
T6	0	4412	0	0
T7	0	5307	0	0
T8	0	219	0	0
T9	0	4436	0	0
T18	0	6	0	0
T19	4798	7	0	0
T20	3255	0	0	0
T21	6830	0	0	0
T22	35155	0	0	0
T23	3329	0	0	0
T24	6923	0	0	0
T25	3448	0	0	0
T26	5171	0	0	0
T27	833	0	0	0
T28	7163	0	0	0