Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3317338	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14581702

1

T21

144

T1

79584

T11

445

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7192526	1			T21	44		T1	42573		T11	90
values[0x0]	5267456	1			T21	59		T1	29266		T11	198
values[0x1]	5439058	1			T21	67		T1	29069		T11	203

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2557726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15341314

1

T21

145

T1

83978

T11

456

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62572	1			T21	1		T1	405		T11	1
valid_sources[0x01]	67420	1			T1	453		T13	1		T16	8
valid_sources[0x02]	65071	1			T1	379		T11	1		T14	1
valid_sources[0x03]	73967	1			T21	1		T1	368		T14	1
valid_sources[0x04]	63268	1			T21	2		T1	409		T11	1
valid_sources[0x05]	61907	1			T1	415		T11	2		T14	1
valid_sources[0x06]	71998	1			T21	1		T1	392		T11	3
valid_sources[0x07]	68445	1			T1	439		T16	4		T17	1
valid_sources[0x08]	65267	1			T21	1		T1	417		T11	3
valid_sources[0x09]	70295	1			T1	409		T11	3		T16	5
valid_sources[0x0a]	63322	1			T21	2		T1	412		T13	1
valid_sources[0x0b]	68741	1			T21	1		T1	421		T11	2
valid_sources[0x0c]	63915	1			T1	377		T11	2		T13	3
valid_sources[0x0d]	63546	1			T1	410		T11	4		T16	3
valid_sources[0x0e]	61773	1			T21	1		T1	355		T11	1
valid_sources[0x0f]	65789	1			T1	412		T11	7		T16	1
valid_sources[0x10]	69425	1			T1	409		T11	3		T13	2
valid_sources[0x11]	63230	1			T1	372		T11	1		T14	1
valid_sources[0x12]	64812	1			T1	364		T11	1		T14	2
valid_sources[0x13]	71645	1			T1	379		T11	12		T14	1
valid_sources[0x14]	157802	1			T1	386		T11	1		T14	1
valid_sources[0x15]	70617	1			T1	386		T16	3		T17	1
valid_sources[0x16]	62204	1			T21	1		T1	418		T16	11
valid_sources[0x17]	68211	1			T21	1		T1	438		T11	2
valid_sources[0x18]	68014	1			T1	416		T14	2		T16	11
valid_sources[0x19]	70291	1			T1	378		T11	2		T14	2
valid_sources[0x1a]	96981	1			T21	1		T1	385		T11	4
valid_sources[0x1b]	61600	1			T1	379		T11	2		T16	7
valid_sources[0x1c]	60867	1			T21	2		T1	383		T11	3
valid_sources[0x1d]	65650	1			T21	1		T1	380		T14	1
valid_sources[0x1e]	64028	1			T1	353		T11	9		T13	1
valid_sources[0x1f]	68134	1			T21	2		T1	356		T11	1
valid_sources[0x20]	74613	1			T21	1		T1	405		T11	4
valid_sources[0x21]	64083	1			T21	1		T1	383		T11	1
valid_sources[0x22]	60125	1			T1	370		T14	1		T16	7
valid_sources[0x23]	70193	1			T1	411		T11	4		T14	2
valid_sources[0x24]	64938	1			T1	376		T11	1		T13	1
valid_sources[0x25]	69081	1			T21	1		T1	431		T11	3
valid_sources[0x26]	64018	1			T21	1		T1	426		T14	1
valid_sources[0x27]	63826	1			T1	399		T13	1		T16	10
valid_sources[0x28]	62425	1			T1	418		T11	5		T16	4
valid_sources[0x29]	67876	1			T21	2		T1	377		T16	1
valid_sources[0x2a]	63873	1			T1	375		T11	5		T14	1
valid_sources[0x2b]	62098	1			T21	4		T1	379		T11	2
valid_sources[0x2c]	72065	1			T1	358		T14	5		T16	5
valid_sources[0x2d]	64746	1			T1	343		T11	5		T14	4
valid_sources[0x2e]	67503	1			T1	389		T11	5		T14	1
valid_sources[0x2f]	106625	1			T1	390		T11	5		T13	1
valid_sources[0x30]	64533	1			T21	1		T1	426		T11	2
valid_sources[0x31]	63747	1			T1	417		T14	1		T16	13
valid_sources[0x32]	64397	1			T1	382		T11	4		T16	7
valid_sources[0x33]	79838	1			T1	367		T11	2		T13	3
valid_sources[0x34]	60549	1			T1	404		T14	3		T16	4
valid_sources[0x35]	69146	1			T1	400		T11	3		T16	8
valid_sources[0x36]	64580	1			T21	2		T1	365		T11	1
valid_sources[0x37]	172711	1			T1	397		T11	2		T14	1
valid_sources[0x38]	178884	1			T21	3		T1	392		T14	1
valid_sources[0x39]	63803	1			T21	1		T1	414		T14	1
valid_sources[0x3a]	64959	1			T1	428		T11	2		T14	1
valid_sources[0x3b]	64522	1			T21	1		T1	363		T13	2
valid_sources[0x3c]	60315	1			T21	1		T1	394		T11	7
valid_sources[0x3d]	61632	1			T1	398		T11	3		T14	1
valid_sources[0x3e]	68186	1			T1	409		T11	6		T14	1
valid_sources[0x3f]	61831	1			T21	2		T1	412		T11	1
valid_sources[0x40]	63871	1			T21	1		T1	402		T11	2
valid_sources[0x41]	73222	1			T21	1		T1	372		T11	1
valid_sources[0x42]	69219	1			T21	1		T1	372		T14	2
valid_sources[0x43]	68877	1			T21	1		T1	362		T11	1
valid_sources[0x44]	58787	1			T21	2		T1	389		T11	7
valid_sources[0x45]	69393	1			T21	2		T1	376		T11	1
valid_sources[0x46]	70926	1			T21	1		T1	374		T11	6
valid_sources[0x47]	68124	1			T1	380		T11	1		T16	2
valid_sources[0x48]	67854	1			T21	1		T1	410		T14	2
valid_sources[0x49]	62395	1			T1	383		T11	7		T14	2
valid_sources[0x4a]	62145	1			T1	367		T11	1		T14	2
valid_sources[0x4b]	66446	1			T21	2		T1	390		T11	4
valid_sources[0x4c]	70381	1			T1	392		T11	2		T14	6
valid_sources[0x4d]	64178	1			T1	386		T14	1		T16	9
valid_sources[0x4e]	70048	1			T21	3		T1	376		T14	3
valid_sources[0x4f]	68994	1			T21	2		T1	396		T11	3
valid_sources[0x50]	133373	1			T21	2		T1	425		T13	1
valid_sources[0x51]	98196	1			T1	417		T16	4		T17	3
valid_sources[0x52]	58829	1			T1	386		T13	3		T14	1
valid_sources[0x53]	68976	1			T21	2		T1	405		T16	4
valid_sources[0x54]	115175	1			T1	380		T14	2		T16	6
valid_sources[0x55]	67633	1			T1	397		T11	2		T13	2
valid_sources[0x56]	65894	1			T1	395		T11	1		T14	1
valid_sources[0x57]	60244	1			T21	1		T1	377		T11	3
valid_sources[0x58]	71552	1			T1	419		T11	3		T13	4
valid_sources[0x59]	71252	1			T21	3		T1	406		T14	1
valid_sources[0x5a]	65736	1			T1	410		T11	1		T13	1
valid_sources[0x5b]	72850	1			T1	397		T11	3		T16	4
valid_sources[0x5c]	68212	1			T1	391		T14	2		T16	5
valid_sources[0x5d]	64124	1			T21	1		T1	366		T11	4
valid_sources[0x5e]	73977	1			T1	387		T11	1		T16	4
valid_sources[0x5f]	62001	1			T21	1		T1	389		T11	3
valid_sources[0x60]	64308	1			T21	3		T1	361		T14	1
valid_sources[0x61]	66947	1			T1	404		T11	2		T13	4
valid_sources[0x62]	63221	1			T1	387		T11	4		T13	1
valid_sources[0x63]	60393	1			T1	410		T11	7		T13	1
valid_sources[0x64]	60880	1			T1	374		T11	4		T13	2
valid_sources[0x65]	71054	1			T1	389		T11	2		T13	1
valid_sources[0x66]	64531	1			T1	406		T14	2		T16	3
valid_sources[0x67]	66294	1			T21	1		T1	396		T11	2
valid_sources[0x68]	70185	1			T21	2		T1	371		T11	3
valid_sources[0x69]	68294	1			T1	413		T11	6		T14	1
valid_sources[0x6a]	61239	1			T21	2		T1	395		T13	5
valid_sources[0x6b]	68827	1			T21	3		T1	428		T14	2
valid_sources[0x6c]	66988	1			T21	1		T1	391		T16	3
valid_sources[0x6d]	68421	1			T1	420		T14	1		T16	5
valid_sources[0x6e]	62678	1			T21	2		T1	380		T11	1
valid_sources[0x6f]	68641	1			T1	420		T11	3		T14	2
valid_sources[0x70]	64527	1			T1	421		T11	5		T14	6
valid_sources[0x71]	64964	1			T1	367		T11	1		T14	1
valid_sources[0x72]	65749	1			T1	386		T14	2		T16	5
valid_sources[0x73]	62228	1			T21	2		T1	363		T11	3
valid_sources[0x74]	58912	1			T1	395		T14	1		T16	2
valid_sources[0x75]	64504	1			T1	365		T11	1		T13	2
valid_sources[0x76]	65116	1			T21	1		T1	383		T14	5
valid_sources[0x77]	63578	1			T21	2		T1	381		T11	6
valid_sources[0x78]	64121	1			T21	1		T1	419		T11	4
valid_sources[0x79]	65850	1			T1	389		T11	2		T14	1
valid_sources[0x7a]	60732	1			T1	353		T11	3		T14	1
valid_sources[0x7b]	62337	1			T1	410		T14	2		T16	9
valid_sources[0x7c]	66838	1			T21	2		T1	364		T11	1
valid_sources[0x7d]	58673	1			T1	372		T14	6		T16	3
valid_sources[0x7e]	62201	1			T1	375		T11	1		T13	2
valid_sources[0x7f]	63828	1			T1	448		T13	2		T14	1
valid_sources[0x80]	66525	1			T1	386		T11	1		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4082278

1

T21

18

T1

21249

T11

44

values[0x0]

all_enables

biggest_size

5250133

1

T21

59

T1

29266

T11

198

values[0x1]

all_enables

biggest_size

5249291

1

T21

67

T1

29069

T11

203