Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	148872730	0	0	0
ctrl_en_input_filter_rd_A	148872730	80509	0	0
intr_ctrl_en_falling_rd_A	148872730	80947	0	0
intr_ctrl_en_lvlhigh_rd_A	148872730	79277	0	0
intr_ctrl_en_lvllow_rd_A	148872730	80701	0	0
intr_ctrl_en_rising_rd_A	148872730	79514	0	0
intr_enable_rd_A	148872730	79742	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	80509	0	0
T1	140011	3779	0	0
T2	35811	144	0	0
T3	0	227	0	0
T4	0	9230	0	0
T5	0	31	0	0
T6	0	234	0	0
T7	0	89	0	0
T8	0	9	0	0
T9	0	2417	0	0
T10	0	2668	0	0
T11	6737	0	0	0
T12	3698	0	0	0
T13	3710	0	0	0
T14	7995	0	0	0
T15	1223	0	0	0
T16	11993	0	0	0
T17	6893	0	0	0
T18	2385	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	80947	0	0
T1	140011	3785	0	0
T2	35811	186	0	0
T3	0	282	0	0
T4	0	10004	0	0
T5	0	77	0	0
T6	0	268	0	0
T7	0	64	0	0
T9	0	2495	0	0
T10	0	2675	0	0
T11	6737	0	0	0
T12	3698	0	0	0
T13	3710	0	0	0
T14	7995	0	0	0
T15	1223	0	0	0
T16	11993	0	0	0
T17	6893	0	0	0
T18	2385	0	0	0
T19	0	1110	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	79277	0	0
T1	140011	3815	0	0
T2	35811	175	0	0
T3	0	223	0	0
T4	0	9415	0	0
T5	0	82	0	0
T6	0	313	0	0
T7	0	62	0	0
T8	0	1	0	0
T9	0	2439	0	0
T11	6737	0	0	0
T12	3698	0	0	0
T13	3710	0	0	0
T14	7995	0	0	0
T15	1223	0	0	0
T16	11993	0	0	0
T17	6893	0	0	0
T18	2385	0	0	0
T20	0	1	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	80701	0	0
T1	140011	3837	0	0
T2	35811	147	0	0
T3	0	215	0	0
T4	0	10093	0	0
T5	0	73	0	0
T6	0	206	0	0
T7	0	68	0	0
T8	0	10	0	0
T9	0	2430	0	0
T10	0	2561	0	0
T11	6737	0	0	0
T12	3698	0	0	0
T13	3710	0	0	0
T14	7995	0	0	0
T15	1223	0	0	0
T16	11993	0	0	0
T17	6893	0	0	0
T18	2385	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	79514	0	0
T1	140011	3886	0	0
T2	35811	210	0	0
T3	0	259	0	0
T4	0	9110	0	0
T5	0	71	0	0
T6	0	247	0	0
T7	0	73	0	0
T9	0	2624	0	0
T10	0	2491	0	0
T11	6737	0	0	0
T12	3698	0	0	0
T13	3710	0	0	0
T14	7995	0	0	0
T15	1223	0	0	0
T16	11993	0	0	0
T17	6893	0	0	0
T18	2385	0	0	0
T19	0	1181	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	148872730	79742	0	0
T1	140011	3797	0	0
T2	35811	185	0	0
T3	0	285	0	0
T4	0	9386	0	0
T5	0	118	0	0
T6	0	221	0	0
T7	0	138	0	0
T8	0	7	0	0
T9	0	2475	0	0
T10	0	2542	0	0
T11	6737	0	0	0
T12	3698	0	0	0
T13	3710	0	0	0
T14	7995	0	0	0
T15	1223	0	0	0
T16	11993	0	0	0
T17	6893	0	0	0
T18	2385	0	0	0