Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3634286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16594317

1

T32

97709

T33

283

T1

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7993267	1			T32	56972		T33	129		T1	4
values[0x0]	6009126	1			T32	34427		T33	86		T1	29
values[0x1]	6226210	1			T32	34827		T33	126		T1	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2784453	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17444150

1

T32

103399

T33

295

T1

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	77158	1			T32	398		T11	412		T12	79
valid_sources[0x01]	78069	1			T32	448		T11	471		T12	64
valid_sources[0x02]	73567	1			T32	522		T11	394		T12	73
valid_sources[0x03]	72369	1			T32	543		T11	462		T12	94
valid_sources[0x04]	84801	1			T32	575		T1	11		T11	428
valid_sources[0x05]	75976	1			T32	462		T11	354		T12	95
valid_sources[0x06]	67460	1			T32	572		T11	460		T12	74
valid_sources[0x07]	188301	1			T32	464		T11	439		T12	81
valid_sources[0x08]	75402	1			T32	513		T11	435		T12	81
valid_sources[0x09]	70326	1			T32	446		T11	422		T12	87
valid_sources[0x0a]	73642	1			T32	433		T11	440		T12	88
valid_sources[0x0b]	72176	1			T32	508		T11	446		T12	93
valid_sources[0x0c]	71540	1			T32	395		T11	431		T12	73
valid_sources[0x0d]	73347	1			T32	480		T11	431		T12	87
valid_sources[0x0e]	78760	1			T32	576		T11	416		T12	88
valid_sources[0x0f]	75614	1			T32	541		T11	423		T12	90
valid_sources[0x10]	110810	1			T32	427		T11	424		T12	72
valid_sources[0x11]	71248	1			T32	575		T11	432		T12	80
valid_sources[0x12]	68111	1			T32	435		T11	404		T12	71
valid_sources[0x13]	67798	1			T32	407		T11	456		T12	72
valid_sources[0x14]	71259	1			T32	443		T11	400		T12	78
valid_sources[0x15]	67692	1			T32	501		T11	410		T12	80
valid_sources[0x16]	73493	1			T32	487		T11	412		T12	85
valid_sources[0x17]	206126	1			T32	496		T11	420		T12	97
valid_sources[0x18]	75214	1			T32	468		T11	385		T12	76
valid_sources[0x19]	70103	1			T32	508		T11	440		T12	91
valid_sources[0x1a]	71499	1			T32	456		T11	427		T12	93
valid_sources[0x1b]	72568	1			T32	487		T11	397		T12	86
valid_sources[0x1c]	72249	1			T32	444		T11	417		T12	67
valid_sources[0x1d]	64839	1			T32	542		T11	428		T12	85
valid_sources[0x1e]	137877	1			T32	480		T11	480		T12	68
valid_sources[0x1f]	76927	1			T32	514		T11	462		T12	94
valid_sources[0x20]	73693	1			T32	524		T11	434		T12	85
valid_sources[0x21]	119843	1			T32	486		T11	440		T12	69
valid_sources[0x22]	71780	1			T32	484		T11	458		T12	95
valid_sources[0x23]	70495	1			T32	462		T11	399		T12	79
valid_sources[0x24]	77950	1			T32	494		T11	398		T12	91
valid_sources[0x25]	186089	1			T32	449		T1	7		T11	437
valid_sources[0x26]	71376	1			T32	514		T11	391		T12	100
valid_sources[0x27]	70551	1			T32	485		T11	375		T12	86
valid_sources[0x28]	116283	1			T32	543		T11	462		T12	85
valid_sources[0x29]	73173	1			T32	414		T11	416		T12	83
valid_sources[0x2a]	67618	1			T32	583		T11	435		T12	84
valid_sources[0x2b]	67386	1			T32	408		T11	414		T12	78
valid_sources[0x2c]	67565	1			T32	452		T11	446		T12	86
valid_sources[0x2d]	66364	1			T32	407		T11	424		T12	83
valid_sources[0x2e]	75724	1			T32	518		T11	413		T12	73
valid_sources[0x2f]	72619	1			T32	486		T11	417		T12	88
valid_sources[0x30]	70990	1			T32	466		T11	445		T12	86
valid_sources[0x31]	72772	1			T32	554		T11	417		T12	65
valid_sources[0x32]	68282	1			T32	553		T11	465		T12	78
valid_sources[0x33]	70108	1			T32	452		T11	430		T12	87
valid_sources[0x34]	72386	1			T32	519		T11	442		T12	97
valid_sources[0x35]	83335	1			T32	465		T11	467		T12	84
valid_sources[0x36]	70984	1			T32	546		T11	441		T12	91
valid_sources[0x37]	69985	1			T32	460		T11	449		T12	97
valid_sources[0x38]	84805	1			T32	552		T11	456		T12	89
valid_sources[0x39]	72980	1			T32	474		T11	414		T12	96
valid_sources[0x3a]	70333	1			T32	439		T11	440		T12	80
valid_sources[0x3b]	72179	1			T32	422		T11	450		T12	87
valid_sources[0x3c]	87635	1			T32	542		T11	401		T12	85
valid_sources[0x3d]	85658	1			T32	509		T11	429		T12	78
valid_sources[0x3e]	68268	1			T32	472		T11	393		T12	77
valid_sources[0x3f]	146239	1			T32	426		T11	432		T12	78
valid_sources[0x40]	65835	1			T32	522		T11	408		T12	80
valid_sources[0x41]	71769	1			T32	531		T11	422		T12	86
valid_sources[0x42]	199756	1			T32	577		T11	425		T12	87
valid_sources[0x43]	74266	1			T32	513		T11	443		T12	83
valid_sources[0x44]	72099	1			T32	611		T11	425		T12	83
valid_sources[0x45]	67331	1			T32	545		T11	419		T12	96
valid_sources[0x46]	71515	1			T32	477		T11	427		T12	84
valid_sources[0x47]	71342	1			T32	569		T11	425		T12	97
valid_sources[0x48]	72048	1			T32	595		T11	442		T12	84
valid_sources[0x49]	76583	1			T32	551		T11	445		T12	66
valid_sources[0x4a]	64305	1			T32	426		T33	341		T11	432
valid_sources[0x4b]	76178	1			T32	439		T11	403		T12	87
valid_sources[0x4c]	73688	1			T32	539		T11	474		T12	86
valid_sources[0x4d]	73544	1			T32	633		T11	415		T12	102
valid_sources[0x4e]	70171	1			T32	557		T11	421		T12	97
valid_sources[0x4f]	75040	1			T32	429		T11	419		T12	78
valid_sources[0x50]	72310	1			T32	643		T11	429		T12	73
valid_sources[0x51]	71827	1			T32	519		T11	433		T12	100
valid_sources[0x52]	74445	1			T32	560		T11	421		T12	76
valid_sources[0x53]	76331	1			T32	501		T11	443		T12	90
valid_sources[0x54]	70348	1			T32	559		T11	437		T12	71
valid_sources[0x55]	211942	1			T32	447		T11	462		T12	92
valid_sources[0x56]	68680	1			T32	537		T11	480		T12	90
valid_sources[0x57]	70691	1			T32	578		T11	429		T12	88
valid_sources[0x58]	71465	1			T32	471		T11	412		T12	76
valid_sources[0x59]	68163	1			T32	475		T11	444		T12	87
valid_sources[0x5a]	64200	1			T32	506		T11	402		T12	99
valid_sources[0x5b]	72131	1			T32	481		T11	424		T12	81
valid_sources[0x5c]	65053	1			T32	489		T11	452		T12	69
valid_sources[0x5d]	72464	1			T32	508		T11	453		T12	87
valid_sources[0x5e]	78570	1			T32	551		T11	440		T12	66
valid_sources[0x5f]	70922	1			T32	569		T11	455		T12	104
valid_sources[0x60]	73210	1			T32	475		T11	437		T12	71
valid_sources[0x61]	74995	1			T32	430		T11	410		T12	90
valid_sources[0x62]	185046	1			T32	548		T11	442		T12	80
valid_sources[0x63]	71461	1			T32	576		T11	462		T12	79
valid_sources[0x64]	73612	1			T32	455		T11	392		T12	84
valid_sources[0x65]	69888	1			T32	497		T11	426		T12	79
valid_sources[0x66]	72803	1			T32	487		T11	430		T12	108
valid_sources[0x67]	71745	1			T32	479		T11	444		T12	102
valid_sources[0x68]	75479	1			T32	444		T11	439		T12	78
valid_sources[0x69]	73798	1			T32	514		T11	450		T12	74
valid_sources[0x6a]	68723	1			T32	476		T11	417		T12	102
valid_sources[0x6b]	71876	1			T32	499		T11	386		T12	64
valid_sources[0x6c]	86375	1			T32	445		T11	437		T12	80
valid_sources[0x6d]	67948	1			T32	438		T11	443		T12	104
valid_sources[0x6e]	74898	1			T32	474		T11	407		T12	87
valid_sources[0x6f]	72457	1			T32	439		T11	421		T12	74
valid_sources[0x70]	73888	1			T32	695		T11	416		T12	68
valid_sources[0x71]	80280	1			T32	448		T11	401		T12	86
valid_sources[0x72]	76796	1			T32	453		T11	442		T12	69
valid_sources[0x73]	71493	1			T32	514		T11	408		T12	69
valid_sources[0x74]	80285	1			T32	491		T11	376		T12	96
valid_sources[0x75]	68921	1			T32	429		T11	431		T12	59
valid_sources[0x76]	73552	1			T32	492		T11	460		T12	97
valid_sources[0x77]	68053	1			T32	386		T11	423		T12	69
valid_sources[0x78]	69992	1			T32	576		T11	397		T12	83
valid_sources[0x79]	70647	1			T32	467		T11	422		T12	72
valid_sources[0x7a]	108081	1			T32	573		T11	443		T12	76
valid_sources[0x7b]	73974	1			T32	511		T11	407		T12	76
valid_sources[0x7c]	76503	1			T32	485		T11	408		T12	68
valid_sources[0x7d]	79146	1			T32	533		T11	411		T12	78
valid_sources[0x7e]	73681	1			T32	453		T11	440		T12	84
valid_sources[0x7f]	69624	1			T32	453		T11	449		T12	92
valid_sources[0x80]	69484	1			T32	495		T11	428		T12	63

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4626294

1

T32

28455

T33

71

T11

24206

values[0x0]

all_enables

biggest_size

5986732

1

T32

34427

T33

86

T1

29

values[0x1]

all_enables

biggest_size

5981291

1

T32

34827

T33

126

T1

19