Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	167934406	0	0	0
ctrl_en_input_filter_rd_A	167934406	54310	0	0
intr_ctrl_en_falling_rd_A	167934406	55080	0	0
intr_ctrl_en_lvlhigh_rd_A	167934406	54071	0	0
intr_ctrl_en_lvllow_rd_A	167934406	54674	0	0
intr_ctrl_en_rising_rd_A	167934406	54629	0	0
intr_enable_rd_A	167934406	54447	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	54310	0	0
T1	2844	6	0	0
T2	0	236	0	0
T3	0	150	0	0
T4	0	2366	0	0
T5	0	1042	0	0
T6	0	2327	0	0
T7	0	2181	0	0
T8	0	5	0	0
T9	0	116	0	0
T10	0	568	0	0
T11	578422	0	0	0
T12	118371	0	0	0
T13	1945	0	0	0
T14	7554	0	0	0
T15	2149	0	0	0
T16	1576	0	0	0
T17	8350	0	0	0
T18	2386	0	0	0
T19	7227	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	55080	0	0
T2	28949	208	0	0
T3	0	187	0	0
T4	0	2255	0	0
T5	0	1020	0	0
T6	0	2346	0	0
T7	0	2253	0	0
T8	0	3	0	0
T9	0	131	0	0
T10	0	608	0	0
T20	0	11628	0	0
T21	8031	0	0	0
T22	5545	0	0	0
T23	6960	0	0	0
T24	1043	0	0	0
T25	10915	0	0	0
T26	4900	0	0	0
T27	1370	0	0	0
T28	1334	0	0	0
T29	739	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	54071	0	0
T2	28949	200	0	0
T3	0	105	0	0
T4	0	2157	0	0
T5	0	952	0	0
T6	0	2277	0	0
T7	0	2428	0	0
T8	0	1	0	0
T9	0	148	0	0
T10	0	517	0	0
T21	8031	0	0	0
T22	5545	0	0	0
T23	6960	0	0	0
T24	1043	0	0	0
T25	10915	0	0	0
T26	4900	0	0	0
T27	1370	0	0	0
T28	1334	0	0	0
T29	739	0	0	0
T30	0	9	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	54674	0	0
T2	28949	191	0	0
T3	0	170	0	0
T4	0	2163	0	0
T5	0	1043	0	0
T6	0	2357	0	0
T7	0	2229	0	0
T9	0	83	0	0
T10	0	509	0	0
T20	0	11543	0	0
T21	8031	0	0	0
T22	5545	0	0	0
T23	6960	0	0	0
T24	1043	0	0	0
T25	10915	0	0	0
T26	4900	0	0	0
T27	1370	0	0	0
T28	1334	0	0	0
T29	739	0	0	0
T30	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	54629	0	0
T2	28949	189	0	0
T3	0	132	0	0
T4	0	2110	0	0
T5	0	994	0	0
T6	0	2324	0	0
T7	0	2232	0	0
T8	0	1	0	0
T9	0	140	0	0
T10	0	491	0	0
T21	8031	0	0	0
T22	5545	0	0	0
T23	6960	0	0	0
T24	1043	0	0	0
T25	10915	0	0	0
T26	4900	0	0	0
T27	1370	0	0	0
T28	1334	0	0	0
T29	739	0	0	0
T30	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167934406	54447	0	0
T2	28949	210	0	0
T3	0	172	0	0
T4	0	2309	0	0
T5	0	1146	0	0
T6	0	2334	0	0
T7	0	2036	0	0
T8	0	10	0	0
T9	0	130	0	0
T10	0	551	0	0
T21	8031	0	0	0
T22	5545	0	0	0
T23	6960	0	0	0
T24	1043	0	0	0
T25	10915	0	0	0
T26	4900	0	0	0
T27	1370	0	0	0
T28	1334	0	0	0
T29	739	0	0	0
T31	0	2	0	0