Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163000785	0	0	0
ctrl_en_input_filter_rd_A	163000785	59814	0	0
intr_ctrl_en_falling_rd_A	163000785	61657	0	0
intr_ctrl_en_lvlhigh_rd_A	163000785	60912	0	0
intr_ctrl_en_lvllow_rd_A	163000785	61098	0	0
intr_ctrl_en_rising_rd_A	163000785	60855	0	0
intr_enable_rd_A	163000785	60640	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	59814	0	0
T1	12442	69	0	0
T2	24285	218	0	0
T3	14375	83	0	0
T4	0	3941	0	0
T5	0	219	0	0
T6	0	181	0	0
T7	0	72	0	0
T8	0	3285	0	0
T9	0	9	0	0
T10	0	14	0	0
T11	55302	0	0	0
T12	4399	0	0	0
T13	25400	0	0	0
T14	43915	0	0	0
T15	4832	0	0	0
T16	78968	0	0	0
T17	6989	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	61657	0	0
T1	12442	95	0	0
T2	24285	167	0	0
T3	14375	127	0	0
T4	0	3703	0	0
T5	0	195	0	0
T6	0	164	0	0
T7	0	51	0	0
T8	0	3222	0	0
T10	0	13	0	0
T11	55302	0	0	0
T12	4399	0	0	0
T13	25400	0	0	0
T14	43915	0	0	0
T15	4832	0	0	0
T16	78968	0	0	0
T17	6989	0	0	0
T18	0	344	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	60912	0	0
T1	0	107	0	0
T2	0	191	0	0
T3	0	156	0	0
T4	0	3956	0	0
T5	0	208	0	0
T6	0	192	0	0
T7	0	53	0	0
T8	0	3362	0	0
T10	0	6	0	0
T19	4222	9	0	0
T20	1232	0	0	0
T21	1539	0	0	0
T22	13618	0	0	0
T23	5980	0	0	0
T24	1303	0	0	0
T25	39709	0	0	0
T26	15878	0	0	0
T27	404764	0	0	0
T28	191779	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	61098	0	0
T1	12442	69	0	0
T2	24285	235	0	0
T3	14375	97	0	0
T4	0	4238	0	0
T5	0	128	0	0
T6	0	197	0	0
T7	0	55	0	0
T8	0	3495	0	0
T9	0	5	0	0
T11	55302	0	0	0
T12	4399	0	0	0
T13	25400	0	0	0
T14	43915	0	0	0
T15	4832	0	0	0
T16	78968	0	0	0
T17	6989	0	0	0
T29	0	1	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	60855	0	0
T1	12442	61	0	0
T2	24285	271	0	0
T3	14375	117	0	0
T4	0	4183	0	0
T5	0	169	0	0
T6	0	171	0	0
T7	0	66	0	0
T8	0	3081	0	0
T9	0	12	0	0
T11	55302	0	0	0
T12	4399	0	0	0
T13	25400	0	0	0
T14	43915	0	0	0
T15	4832	0	0	0
T16	78968	0	0	0
T17	6989	0	0	0
T29	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163000785	60640	0	0
T1	12442	101	0	0
T2	24285	208	0	0
T3	14375	98	0	0
T4	0	3930	0	0
T5	0	140	0	0
T6	0	225	0	0
T7	0	79	0	0
T8	0	3131	0	0
T11	55302	0	0	0
T12	4399	0	0	0
T13	25400	0	0	0
T14	43915	0	0	0
T15	4832	0	0	0
T16	78968	0	0	0
T17	6989	0	0	0
T29	0	5	0	0
T30	0	2	0	0