Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2719187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11928680

1

T22

355

T23

269

T24

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5910947	1			T22	92		T23	22		T24	1
values[0x0]	4297595	1			T22	155		T23	136		T24	8
values[0x1]	4439325	1			T22	163		T23	122		T24	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2096733	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12551134

1

T22

370

T23

269

T24

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52774	1			T26	4		T27	3		T29	8
valid_sources[0x01]	51029	1			T22	3		T23	3		T26	3
valid_sources[0x02]	52224	1			T22	2		T23	2		T26	14
valid_sources[0x03]	57555	1			T22	1		T23	1		T26	5
valid_sources[0x04]	51094	1			T22	4		T23	3		T26	4
valid_sources[0x05]	59040	1			T22	1		T23	3		T26	2
valid_sources[0x06]	52582	1			T22	1		T26	4		T27	11
valid_sources[0x07]	55360	1			T22	1		T26	4		T27	6
valid_sources[0x08]	53992	1			T22	2		T23	1		T27	6
valid_sources[0x09]	58352	1			T22	1		T23	1		T26	1
valid_sources[0x0a]	52991	1			T22	1		T23	4		T26	3
valid_sources[0x0b]	50258	1			T22	1		T26	1		T27	6
valid_sources[0x0c]	56158	1			T22	3		T23	2		T26	6
valid_sources[0x0d]	55502	1			T22	3		T23	1		T26	3
valid_sources[0x0e]	50819	1			T22	1		T26	5		T27	9
valid_sources[0x0f]	55613	1			T22	1		T26	2		T27	5
valid_sources[0x10]	54308	1			T22	3		T26	3		T27	7
valid_sources[0x11]	55908	1			T22	2		T26	2		T27	5
valid_sources[0x12]	52950	1			T27	12		T110	2		T115	1
valid_sources[0x13]	51795	1			T23	3		T26	5		T27	6
valid_sources[0x14]	54032	1			T22	1		T23	2		T26	4
valid_sources[0x15]	52888	1			T22	1		T23	1		T27	15
valid_sources[0x16]	54214	1			T22	1		T23	1		T26	2
valid_sources[0x17]	51604	1			T22	1		T23	3		T26	7
valid_sources[0x18]	51425	1			T22	3		T23	1		T26	2
valid_sources[0x19]	51780	1			T22	1		T26	2		T27	7
valid_sources[0x1a]	50348	1			T22	5		T23	1		T27	15
valid_sources[0x1b]	53955	1			T26	2		T27	3		T29	11
valid_sources[0x1c]	50254	1			T22	1		T23	3		T26	5
valid_sources[0x1d]	56705	1			T22	1		T23	2		T26	3
valid_sources[0x1e]	52026	1			T22	1		T23	1		T26	2
valid_sources[0x1f]	52596	1			T23	2		T26	4		T27	7
valid_sources[0x20]	53449	1			T22	4		T26	6		T27	10
valid_sources[0x21]	54826	1			T22	3		T23	2		T26	6
valid_sources[0x22]	57142	1			T22	2		T23	3		T26	5
valid_sources[0x23]	50816	1			T22	3		T26	12		T27	12
valid_sources[0x24]	55788	1			T22	1		T23	1		T26	7
valid_sources[0x25]	50180	1			T26	2		T27	3		T29	3
valid_sources[0x26]	52591	1			T22	1		T26	8		T27	13
valid_sources[0x27]	265780	1			T22	1		T23	1		T26	2
valid_sources[0x28]	60006	1			T22	1		T26	7		T27	10
valid_sources[0x29]	51800	1			T22	1		T23	6		T26	2
valid_sources[0x2a]	54864	1			T22	1		T23	1		T26	2
valid_sources[0x2b]	50566	1			T22	1		T23	4		T26	6
valid_sources[0x2c]	51269	1			T22	3		T23	1		T26	4
valid_sources[0x2d]	50695	1			T22	2		T26	1		T27	7
valid_sources[0x2e]	50220	1			T26	4		T27	9		T110	3
valid_sources[0x2f]	55421	1			T22	1		T23	3		T26	5
valid_sources[0x30]	51668	1			T26	4		T27	15		T28	1
valid_sources[0x31]	54984	1			T22	3		T23	1		T26	5
valid_sources[0x32]	53944	1			T22	2		T26	2		T27	14
valid_sources[0x33]	60433	1			T22	2		T26	2		T27	6
valid_sources[0x34]	52027	1			T22	1		T26	3		T27	15
valid_sources[0x35]	56329	1			T26	6		T27	4		T28	2
valid_sources[0x36]	53175	1			T22	2		T24	3		T26	1
valid_sources[0x37]	51694	1			T26	4		T27	7		T28	1
valid_sources[0x38]	55345	1			T22	2		T23	4		T26	3
valid_sources[0x39]	50999	1			T22	3		T26	2		T27	10
valid_sources[0x3a]	58416	1			T22	3		T23	3		T26	4
valid_sources[0x3b]	56890	1			T22	7		T23	1		T26	4
valid_sources[0x3c]	51106	1			T26	3		T27	2		T29	8
valid_sources[0x3d]	51169	1			T27	11		T29	1		T30	2
valid_sources[0x3e]	59033	1			T22	4		T23	1		T26	3
valid_sources[0x3f]	54625	1			T22	2		T26	6		T27	11
valid_sources[0x40]	52969	1			T22	4		T23	1		T26	3
valid_sources[0x41]	50858	1			T22	2		T23	1		T26	3
valid_sources[0x42]	52077	1			T23	4		T26	2		T27	10
valid_sources[0x43]	54995	1			T22	2		T23	3		T26	3
valid_sources[0x44]	51658	1			T22	6		T23	2		T26	5
valid_sources[0x45]	56352	1			T22	2		T23	4		T26	8
valid_sources[0x46]	52263	1			T22	1		T23	4		T27	10
valid_sources[0x47]	50248	1			T22	2		T26	7		T27	20
valid_sources[0x48]	49814	1			T22	1		T23	2		T26	3
valid_sources[0x49]	52026	1			T26	3		T27	10		T30	1
valid_sources[0x4a]	58414	1			T22	3		T23	3		T26	1
valid_sources[0x4b]	53721	1			T22	1		T26	2		T27	8
valid_sources[0x4c]	50383	1			T23	1		T26	3		T27	9
valid_sources[0x4d]	50160	1			T22	1		T27	5		T28	2
valid_sources[0x4e]	51741	1			T26	3		T27	8		T28	2
valid_sources[0x4f]	56799	1			T22	1		T26	4		T27	6
valid_sources[0x50]	50499	1			T22	2		T26	3		T27	10
valid_sources[0x51]	50077	1			T22	2		T26	1		T27	8
valid_sources[0x52]	53868	1			T22	4		T23	4		T26	1
valid_sources[0x53]	53502	1			T23	2		T26	3		T27	1
valid_sources[0x54]	53960	1			T26	5		T27	5		T28	3
valid_sources[0x55]	52646	1			T22	1		T23	2		T26	3
valid_sources[0x56]	142613	1			T26	1		T27	2		T29	36
valid_sources[0x57]	54073	1			T22	1		T23	4		T26	4
valid_sources[0x58]	50493	1			T23	1		T26	4		T27	12
valid_sources[0x59]	60419	1			T22	2		T26	5		T27	8
valid_sources[0x5a]	55304	1			T22	2		T26	4		T27	8
valid_sources[0x5b]	49974	1			T22	4		T26	6		T27	8
valid_sources[0x5c]	55497	1			T23	1		T26	2		T27	4
valid_sources[0x5d]	53491	1			T26	1		T27	10		T28	1
valid_sources[0x5e]	50837	1			T22	4		T23	1		T26	1
valid_sources[0x5f]	51613	1			T22	2		T23	2		T26	5
valid_sources[0x60]	51942	1			T22	2		T26	3		T27	7
valid_sources[0x61]	52480	1			T22	2		T26	4		T27	4
valid_sources[0x62]	52485	1			T22	3		T23	1		T26	1
valid_sources[0x63]	52761	1			T22	1		T24	9		T26	1
valid_sources[0x64]	53220	1			T22	2		T26	5		T27	11
valid_sources[0x65]	54202	1			T22	2		T26	5		T27	4
valid_sources[0x66]	51831	1			T22	1		T23	2		T26	3
valid_sources[0x67]	57319	1			T22	3		T23	7		T26	3
valid_sources[0x68]	51176	1			T22	2		T23	1		T26	11
valid_sources[0x69]	49744	1			T23	1		T26	7		T27	6
valid_sources[0x6a]	51509	1			T22	2		T23	5		T26	4
valid_sources[0x6b]	52877	1			T22	2		T26	3		T27	7
valid_sources[0x6c]	51426	1			T22	1		T26	8		T27	9
valid_sources[0x6d]	52621	1			T22	2		T26	5		T27	8
valid_sources[0x6e]	52037	1			T22	2		T26	3		T27	8
valid_sources[0x6f]	52301	1			T22	2		T27	3		T28	2
valid_sources[0x70]	54198	1			T22	1		T23	2		T26	2
valid_sources[0x71]	53746	1			T22	1		T26	4		T27	12
valid_sources[0x72]	53559	1			T26	1		T27	11		T28	1
valid_sources[0x73]	51021	1			T22	3		T26	1		T27	9
valid_sources[0x74]	54109	1			T23	1		T26	4		T27	5
valid_sources[0x75]	75017	1			T22	2		T23	1		T26	5
valid_sources[0x76]	52452	1			T26	3		T27	9		T29	19
valid_sources[0x77]	56132	1			T23	5		T26	2		T27	22
valid_sources[0x78]	56918	1			T23	1		T26	4		T27	9
valid_sources[0x79]	53748	1			T22	3		T26	3		T27	7
valid_sources[0x7a]	54047	1			T26	2		T27	3		T28	1
valid_sources[0x7b]	50093	1			T22	2		T23	1		T26	2
valid_sources[0x7c]	50379	1			T22	1		T26	3		T27	8
valid_sources[0x7d]	58792	1			T26	4		T27	10		T28	2
valid_sources[0x7e]	151260	1			T23	2		T26	2		T27	12
valid_sources[0x7f]	50190	1			T22	1		T26	4		T27	14
valid_sources[0x80]	50169	1			T26	4		T27	8		T30	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3363413

1

T22

37

T23

11

T25

73

values[0x0]

all_enables

biggest_size

4283016

1

T22

155

T23

136

T24

4

values[0x1]

all_enables

biggest_size

4282251

1

T22

163

T23

122

T24

1