Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	123514627	0	0	0
ctrl_en_input_filter_rd_A	123514627	49489	0	0
intr_ctrl_en_falling_rd_A	123514627	50151	0	0
intr_ctrl_en_lvlhigh_rd_A	123514627	49961	0	0
intr_ctrl_en_lvllow_rd_A	123514627	49940	0	0
intr_ctrl_en_rising_rd_A	123514627	50188	0	0
intr_enable_rd_A	123514627	49596	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	49489	0	0
T1	18055	75	0	0
T2	13782	154	0	0
T3	0	220	0	0
T4	0	6603	0	0
T5	0	283	0	0
T6	0	438	0	0
T7	0	153	0	0
T8	0	2894	0	0
T9	0	3	0	0
T10	0	9	0	0
T11	965	0	0	0
T12	5712	0	0	0
T13	3569	0	0	0
T14	6579	0	0	0
T15	10924	0	0	0
T16	7084	0	0	0
T17	3893	0	0	0
T18	6286	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	50151	0	0
T1	18055	116	0	0
T2	13782	107	0	0
T3	0	191	0	0
T4	0	6322	0	0
T5	0	247	0	0
T6	0	378	0	0
T7	0	204	0	0
T8	0	2669	0	0
T9	0	7	0	0
T10	0	7	0	0
T11	965	0	0	0
T12	5712	0	0	0
T13	3569	0	0	0
T14	6579	0	0	0
T15	10924	0	0	0
T16	7084	0	0	0
T17	3893	0	0	0
T18	6286	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	49961	0	0
T1	18055	65	0	0
T2	13782	119	0	0
T3	0	227	0	0
T4	0	6381	0	0
T5	0	253	0	0
T6	0	393	0	0
T7	0	235	0	0
T8	0	2839	0	0
T10	0	9	0	0
T11	965	0	0	0
T12	5712	0	0	0
T13	3569	0	0	0
T14	6579	0	0	0
T15	10924	0	0	0
T16	7084	0	0	0
T17	3893	0	0	0
T18	6286	0	0	0
T19	0	4996	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	49940	0	0
T1	18055	121	0	0
T2	13782	122	0	0
T3	0	290	0	0
T4	0	6388	0	0
T5	0	285	0	0
T6	0	293	0	0
T7	0	186	0	0
T8	0	2808	0	0
T9	0	4	0	0
T11	965	0	0	0
T12	5712	0	0	0
T13	3569	0	0	0
T14	6579	0	0	0
T15	10924	0	0	0
T16	7084	0	0	0
T17	3893	0	0	0
T18	6286	0	0	0
T20	0	6	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	50188	0	0
T1	18055	78	0	0
T2	13782	100	0	0
T3	0	219	0	0
T4	0	6381	0	0
T5	0	282	0	0
T6	0	330	0	0
T7	0	218	0	0
T8	0	2885	0	0
T9	0	1	0	0
T11	965	0	0	0
T12	5712	0	0	0
T13	3569	0	0	0
T14	6579	0	0	0
T15	10924	0	0	0
T16	7084	0	0	0
T17	3893	0	0	0
T18	6286	0	0	0
T19	0	4955	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123514627	49596	0	0
T1	18055	92	0	0
T2	13782	150	0	0
T3	0	243	0	0
T4	0	6206	0	0
T5	0	242	0	0
T6	0	284	0	0
T7	0	203	0	0
T8	0	2522	0	0
T9	0	12	0	0
T11	965	0	0	0
T12	5712	0	0	0
T13	3569	0	0	0
T14	6579	0	0	0
T15	10924	0	0	0
T16	7084	0	0	0
T17	3893	0	0	0
T18	6286	0	0	0
T21	0	2	0	0