Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3709594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16355137

1

T1

3307

T2

1560

T11

120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8076710	1			T1	2302		T2	1020		T11	39
values[0x0]	5891516	1			T1	1091		T2	521		T11	51
values[0x1]	6096505	1			T1	1035		T2	520		T11	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2854928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17209803

1

T1

3544

T2

1654

T11

122

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	74753	1			T1	18		T2	6		T12	16
valid_sources[0x01]	131756	1			T1	13		T2	3		T12	23
valid_sources[0x02]	68994	1			T1	15		T2	12		T11	1
valid_sources[0x03]	74073	1			T1	8		T2	5		T11	1
valid_sources[0x04]	73015	1			T1	20		T2	7		T11	1
valid_sources[0x05]	79748	1			T1	21		T2	6		T12	22
valid_sources[0x06]	78354	1			T1	19		T2	6		T11	1
valid_sources[0x07]	76312	1			T1	21		T2	22		T12	14
valid_sources[0x08]	69231	1			T1	17		T2	16		T12	10
valid_sources[0x09]	71558	1			T1	10		T2	12		T11	1
valid_sources[0x0a]	81493	1			T1	12		T2	6		T11	1
valid_sources[0x0b]	73059	1			T1	6		T2	13		T11	1
valid_sources[0x0c]	71359	1			T1	18		T2	8		T12	18
valid_sources[0x0d]	76679	1			T1	21		T2	16		T12	13
valid_sources[0x0e]	73879	1			T1	21		T2	10		T12	10
valid_sources[0x0f]	70821	1			T1	33		T2	7		T11	1
valid_sources[0x10]	76838	1			T1	18		T2	12		T11	1
valid_sources[0x11]	96479	1			T1	21		T2	7		T11	1
valid_sources[0x12]	73884	1			T1	5		T2	6		T12	15
valid_sources[0x13]	72541	1			T1	12		T2	14		T11	1
valid_sources[0x14]	75027	1			T1	11		T2	10		T11	1
valid_sources[0x15]	73055	1			T1	18		T2	6		T12	21
valid_sources[0x16]	80721	1			T1	38		T2	7		T12	13
valid_sources[0x17]	74143	1			T1	24		T2	11		T11	1
valid_sources[0x18]	73457	1			T1	17		T2	6		T11	2
valid_sources[0x19]	76398	1			T1	5		T2	5		T12	11
valid_sources[0x1a]	76044	1			T1	20		T2	7		T12	16
valid_sources[0x1b]	82810	1			T1	24		T2	7		T11	1
valid_sources[0x1c]	76712	1			T1	30		T2	6		T11	1
valid_sources[0x1d]	72954	1			T1	7		T2	9		T12	15
valid_sources[0x1e]	75053	1			T1	27		T2	8		T12	13
valid_sources[0x1f]	75424	1			T1	30		T2	6		T12	14
valid_sources[0x20]	75261	1			T1	21		T2	8		T11	1
valid_sources[0x21]	78170	1			T1	10		T2	7		T12	17
valid_sources[0x22]	76778	1			T1	30		T2	6		T11	2
valid_sources[0x23]	69519	1			T1	8		T2	6		T12	13
valid_sources[0x24]	73793	1			T1	26		T2	5		T12	17
valid_sources[0x25]	71948	1			T1	20		T2	7		T11	1
valid_sources[0x26]	67278	1			T1	23		T2	9		T12	17
valid_sources[0x27]	79482	1			T1	24		T2	8		T12	13
valid_sources[0x28]	75056	1			T1	12		T2	8		T12	11
valid_sources[0x29]	71637	1			T1	17		T2	11		T12	15
valid_sources[0x2a]	73523	1			T1	23		T2	10		T11	3
valid_sources[0x2b]	78824	1			T1	33		T2	4		T12	18
valid_sources[0x2c]	73453	1			T1	14		T2	6		T11	2
valid_sources[0x2d]	75362	1			T1	8		T2	7		T11	1
valid_sources[0x2e]	78108	1			T1	14		T2	8		T11	2
valid_sources[0x2f]	71210	1			T1	19		T2	10		T11	1
valid_sources[0x30]	79986	1			T1	21		T2	15		T12	15
valid_sources[0x31]	76735	1			T1	9		T2	6		T12	11
valid_sources[0x32]	72826	1			T1	10		T2	7		T11	1
valid_sources[0x33]	77640	1			T1	10		T2	6		T12	16
valid_sources[0x34]	89564	1			T1	16		T2	5		T11	1
valid_sources[0x35]	85130	1			T1	8		T2	6		T11	2
valid_sources[0x36]	71283	1			T1	26		T2	12		T12	6
valid_sources[0x37]	87735	1			T1	21		T2	9		T11	1
valid_sources[0x38]	69134	1			T1	16		T2	13		T11	1
valid_sources[0x39]	71771	1			T1	24		T2	5		T12	15
valid_sources[0x3a]	76023	1			T1	11		T2	10		T11	1
valid_sources[0x3b]	74104	1			T1	11		T2	4		T12	12
valid_sources[0x3c]	79473	1			T1	12		T2	9		T12	15
valid_sources[0x3d]	74774	1			T1	19		T2	10		T11	3
valid_sources[0x3e]	70880	1			T1	12		T2	7		T12	26
valid_sources[0x3f]	77150	1			T1	29		T2	12		T12	10
valid_sources[0x40]	73300	1			T1	8		T2	11		T12	13
valid_sources[0x41]	75315	1			T1	15		T2	12		T11	2
valid_sources[0x42]	69389	1			T1	19		T2	7		T11	2
valid_sources[0x43]	73042	1			T1	20		T2	10		T12	16
valid_sources[0x44]	76030	1			T1	39		T2	12		T12	16
valid_sources[0x45]	71420	1			T1	17		T2	13		T12	21
valid_sources[0x46]	75484	1			T1	7		T2	9		T12	12
valid_sources[0x47]	73095	1			T1	25		T2	4		T12	8
valid_sources[0x48]	160925	1			T1	28		T2	7		T12	15
valid_sources[0x49]	75758	1			T1	25		T2	7		T12	13
valid_sources[0x4a]	75997	1			T1	26		T2	6		T12	14
valid_sources[0x4b]	76816	1			T1	22		T2	14		T11	1
valid_sources[0x4c]	70707	1			T1	24		T2	9		T11	1
valid_sources[0x4d]	74631	1			T1	9		T2	8		T12	17
valid_sources[0x4e]	75880	1			T1	44		T2	3		T11	1
valid_sources[0x4f]	69525	1			T1	31		T2	9		T12	15
valid_sources[0x50]	69675	1			T1	8		T2	9		T12	11
valid_sources[0x51]	70405	1			T1	17		T2	6		T11	2
valid_sources[0x52]	80049	1			T1	24		T2	6		T12	8
valid_sources[0x53]	75379	1			T1	3		T2	11		T12	9
valid_sources[0x54]	73074	1			T1	23		T2	2		T12	11
valid_sources[0x55]	75112	1			T1	8		T2	7		T12	16
valid_sources[0x56]	74746	1			T1	17		T2	5		T12	15
valid_sources[0x57]	73368	1			T1	5		T2	6		T12	16
valid_sources[0x58]	72613	1			T1	16		T2	12		T11	1
valid_sources[0x59]	76431	1			T1	23		T2	15		T12	6
valid_sources[0x5a]	70863	1			T1	28		T2	8		T12	16
valid_sources[0x5b]	82264	1			T1	24		T2	6		T12	12
valid_sources[0x5c]	98322	1			T1	2		T2	8		T12	13
valid_sources[0x5d]	82058	1			T1	23		T2	3		T12	15
valid_sources[0x5e]	79952	1			T1	14		T2	6		T12	22
valid_sources[0x5f]	74053	1			T1	20		T2	7		T11	2
valid_sources[0x60]	71440	1			T1	32		T2	2		T11	3
valid_sources[0x61]	72123	1			T1	12		T2	11		T12	5
valid_sources[0x62]	81673	1			T1	14		T2	10		T12	10
valid_sources[0x63]	80307	1			T1	37		T2	8		T11	2
valid_sources[0x64]	72553	1			T1	6		T2	4		T11	1
valid_sources[0x65]	73695	1			T1	12		T2	5		T12	15
valid_sources[0x66]	78947	1			T1	9		T2	7		T12	10
valid_sources[0x67]	79009	1			T1	11		T2	13		T11	1
valid_sources[0x68]	83008	1			T1	16		T2	9		T11	1
valid_sources[0x69]	74483	1			T1	23		T2	2		T12	8
valid_sources[0x6a]	78254	1			T1	16		T2	7		T12	22
valid_sources[0x6b]	78584	1			T1	18		T2	4		T11	1
valid_sources[0x6c]	70036	1			T1	23		T2	6		T11	1
valid_sources[0x6d]	74634	1			T1	24		T2	14		T12	16
valid_sources[0x6e]	72283	1			T1	14		T2	13		T11	1
valid_sources[0x6f]	72414	1			T1	17		T2	9		T12	14
valid_sources[0x70]	80762	1			T1	11		T2	7		T11	1
valid_sources[0x71]	78506	1			T1	29		T2	5		T12	11
valid_sources[0x72]	73981	1			T1	8		T2	9		T12	18
valid_sources[0x73]	77189	1			T1	11		T2	6		T11	1
valid_sources[0x74]	75024	1			T1	20		T2	10		T11	1
valid_sources[0x75]	77617	1			T1	20		T2	13		T12	18
valid_sources[0x76]	74802	1			T1	10		T2	4		T12	12
valid_sources[0x77]	69211	1			T1	14		T2	16		T11	1
valid_sources[0x78]	74538	1			T1	12		T2	8		T12	13
valid_sources[0x79]	72566	1			T1	10		T2	7		T12	11
valid_sources[0x7a]	100285	1			T1	11		T2	6		T11	1
valid_sources[0x7b]	76308	1			T1	16		T2	2		T12	13
valid_sources[0x7c]	70731	1			T1	15		T2	3		T12	14
valid_sources[0x7d]	81403	1			T1	13		T2	8		T12	18
valid_sources[0x7e]	71820	1			T1	15		T2	12		T12	12
valid_sources[0x7f]	78043	1			T1	25		T2	8		T12	12
valid_sources[0x80]	75195	1			T1	19		T2	8		T12	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4610484

1

T1

1181

T2

519

T11

24

values[0x0]

all_enables

biggest_size

5871140

1

T1

1091

T2

521

T11

51

values[0x1]

all_enables

biggest_size

5873513

1

T1

1035

T2

520

T11

45