Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	158897523	0	0	0
ctrl_en_input_filter_rd_A	158897523	63878	0	0
intr_ctrl_en_falling_rd_A	158897523	66380	0	0
intr_ctrl_en_lvlhigh_rd_A	158897523	64088	0	0
intr_ctrl_en_lvllow_rd_A	158897523	67431	0	0
intr_ctrl_en_rising_rd_A	158897523	64004	0	0
intr_enable_rd_A	158897523	63998	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	63878	0	0
T1	48233	290	0	0
T2	23280	146	0	0
T3	0	193	0	0
T4	0	252	0	0
T5	0	261	0	0
T6	0	3331	0	0
T7	0	87	0	0
T8	0	227	0	0
T9	0	4318	0	0
T10	0	1811	0	0
T11	1814	0	0	0
T12	53583	0	0	0
T13	7243	0	0	0
T14	20825	0	0	0
T15	2818	0	0	0
T16	109290	0	0	0
T17	2380	0	0	0
T18	2314	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	66380	0	0
T1	48233	316	0	0
T2	23280	214	0	0
T3	0	172	0	0
T4	0	217	0	0
T5	0	330	0	0
T6	0	3352	0	0
T7	0	86	0	0
T8	0	224	0	0
T9	0	4251	0	0
T10	0	1989	0	0
T11	1814	0	0	0
T12	53583	0	0	0
T13	7243	0	0	0
T14	20825	0	0	0
T15	2818	0	0	0
T16	109290	0	0	0
T17	2380	0	0	0
T18	2314	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	64088	0	0
T1	48233	380	0	0
T2	23280	148	0	0
T3	0	174	0	0
T4	0	178	0	0
T5	0	366	0	0
T6	0	3397	0	0
T7	0	80	0	0
T8	0	309	0	0
T9	0	4123	0	0
T10	0	1845	0	0
T11	1814	0	0	0
T12	53583	0	0	0
T13	7243	0	0	0
T14	20825	0	0	0
T15	2818	0	0	0
T16	109290	0	0	0
T17	2380	0	0	0
T18	2314	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	67431	0	0
T1	48233	432	0	0
T2	23280	189	0	0
T3	0	149	0	0
T4	0	233	0	0
T5	0	330	0	0
T6	0	3355	0	0
T7	0	110	0	0
T8	0	253	0	0
T9	0	4356	0	0
T10	0	1935	0	0
T11	1814	0	0	0
T12	53583	0	0	0
T13	7243	0	0	0
T14	20825	0	0	0
T15	2818	0	0	0
T16	109290	0	0	0
T17	2380	0	0	0
T18	2314	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	64004	0	0
T1	48233	359	0	0
T2	23280	140	0	0
T3	0	181	0	0
T4	0	193	0	0
T5	0	343	0	0
T6	0	3633	0	0
T7	0	98	0	0
T8	0	198	0	0
T9	0	4123	0	0
T10	0	1801	0	0
T11	1814	0	0	0
T12	53583	0	0	0
T13	7243	0	0	0
T14	20825	0	0	0
T15	2818	0	0	0
T16	109290	0	0	0
T17	2380	0	0	0
T18	2314	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158897523	63998	0	0
T1	48233	364	0	0
T2	23280	166	0	0
T3	0	181	0	0
T4	0	218	0	0
T5	0	286	0	0
T6	0	3476	0	0
T7	0	90	0	0
T8	0	186	0	0
T9	0	4173	0	0
T10	0	1925	0	0
T11	1814	0	0	0
T12	53583	0	0	0
T13	7243	0	0	0
T14	20825	0	0	0
T15	2818	0	0	0
T16	109290	0	0	0
T17	2380	0	0	0
T18	2314	0	0	0