Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	201698501	0	0	0
ctrl_en_input_filter_rd_A	201698501	105522	0	0
intr_ctrl_en_falling_rd_A	201698501	109110	0	0
intr_ctrl_en_lvlhigh_rd_A	201698501	105211	0	0
intr_ctrl_en_lvllow_rd_A	201698501	107764	0	0
intr_ctrl_en_rising_rd_A	201698501	104994	0	0
intr_enable_rd_A	201698501	104807	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	105522	0	0
T1	149424	5921	0	0
T2	189238	7072	0	0
T3	786977	2111	0	0
T4	0	144	0	0
T5	0	7901	0	0
T6	0	3723	0	0
T7	0	49	0	0
T8	0	5770	0	0
T9	0	13	0	0
T10	0	7161	0	0
T11	2836	0	0	0
T12	5729	0	0	0
T13	3607	0	0	0
T14	4225	0	0	0
T15	5182	0	0	0
T16	6850	0	0	0
T17	2335	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	109110	0	0
T1	149424	6120	0	0
T2	189238	6621	0	0
T3	786977	2186	0	0
T4	0	123	0	0
T5	0	7732	0	0
T6	0	3560	0	0
T7	0	41	0	0
T8	0	6254	0	0
T9	0	6	0	0
T11	2836	0	0	0
T12	5729	0	0	0
T13	3607	0	0	0
T14	4225	0	0	0
T15	5182	0	0	0
T16	6850	0	0	0
T17	2335	0	0	0
T18	0	4	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	105211	0	0
T1	149424	5891	0	0
T2	189238	7069	0	0
T3	786977	2007	0	0
T4	0	187	0	0
T5	0	7497	0	0
T6	0	3605	0	0
T7	0	53	0	0
T8	0	5844	0	0
T9	0	15	0	0
T11	2836	0	0	0
T12	5729	0	0	0
T13	3607	0	0	0
T14	4225	0	0	0
T15	5182	0	0	0
T16	6850	0	0	0
T17	2335	0	0	0
T18	0	8	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	107764	0	0
T1	149424	5735	0	0
T2	189238	6874	0	0
T3	786977	2163	0	0
T4	0	107	0	0
T5	0	7240	0	0
T6	0	3842	0	0
T7	0	39	0	0
T8	0	5813	0	0
T10	0	6805	0	0
T11	2836	0	0	0
T12	5729	0	0	0
T13	3607	0	0	0
T14	4225	0	0	0
T15	5182	0	0	0
T16	6850	0	0	0
T17	2335	0	0	0
T19	0	1387	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	104994	0	0
T1	149424	5451	0	0
T2	189238	6985	0	0
T3	786977	2278	0	0
T4	0	117	0	0
T5	0	8053	0	0
T6	0	3648	0	0
T7	0	20	0	0
T8	0	5758	0	0
T9	0	9	0	0
T11	2836	0	0	0
T12	5729	0	0	0
T13	3607	0	0	0
T14	4225	0	0	0
T15	5182	0	0	0
T16	6850	0	0	0
T17	2335	0	0	0
T18	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201698501	104807	0	0
T1	149424	5761	0	0
T2	189238	6587	0	0
T3	786977	2271	0	0
T4	0	129	0	0
T5	0	8109	0	0
T6	0	3699	0	0
T7	0	36	0	0
T8	0	5845	0	0
T10	0	6618	0	0
T11	2836	0	0	0
T12	5729	0	0	0
T13	3607	0	0	0
T14	4225	0	0	0
T15	5182	0	0	0
T16	6850	0	0	0
T17	2335	0	0	0
T18	0	6	0	0