Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3672884	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16404083

1

T30

7

T31

172

T32

3117

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8020070	1			T30	1		T31	195		T32	4822
values[0x0]	5924124	1			T30	10		T31	37		T32	353
values[0x1]	6132773	1			T30	16		T31	41		T32	356

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2823120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17253847

1

T30

13

T31

191

T32

3591

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	192464	1			T32	23		T33	13		T35	2
valid_sources[0x01]	68072	1			T32	21		T33	14		T35	1
valid_sources[0x02]	79094	1			T32	30		T33	14		T35	1
valid_sources[0x03]	76175	1			T31	14		T32	29		T33	24
valid_sources[0x04]	73088	1			T32	20		T33	11		T35	2
valid_sources[0x05]	75682	1			T32	16		T33	19		T37	4073
valid_sources[0x06]	79081	1			T32	15		T33	8		T37	4275
valid_sources[0x07]	75509	1			T31	14		T32	19		T33	6
valid_sources[0x08]	80723	1			T32	13		T33	11		T37	4153
valid_sources[0x09]	72312	1			T31	5		T32	19		T33	20
valid_sources[0x0a]	80194	1			T32	31		T33	16		T35	1
valid_sources[0x0b]	71780	1			T32	21		T33	18		T37	4151
valid_sources[0x0c]	75350	1			T32	28		T33	15		T37	4267
valid_sources[0x0d]	72165	1			T32	20		T33	18		T35	2
valid_sources[0x0e]	72984	1			T32	15		T33	20		T37	4181
valid_sources[0x0f]	74425	1			T31	2		T32	18		T33	7
valid_sources[0x10]	72096	1			T32	20		T33	16		T37	4261
valid_sources[0x11]	69757	1			T31	15		T32	20		T33	17
valid_sources[0x12]	74928	1			T32	19		T33	25		T37	4154
valid_sources[0x13]	69514	1			T32	25		T33	17		T37	4111
valid_sources[0x14]	78588	1			T32	18		T33	15		T37	4175
valid_sources[0x15]	74050	1			T32	17		T33	15		T36	9
valid_sources[0x16]	120254	1			T32	34		T33	19		T37	4254
valid_sources[0x17]	72115	1			T32	23		T33	13		T35	1
valid_sources[0x18]	77090	1			T32	20		T33	19		T35	1
valid_sources[0x19]	69671	1			T31	2		T32	20		T33	17
valid_sources[0x1a]	71822	1			T31	3		T32	24		T33	26
valid_sources[0x1b]	70039	1			T32	20		T33	15		T37	4170
valid_sources[0x1c]	76706	1			T31	1		T32	19		T33	16
valid_sources[0x1d]	73306	1			T32	18		T33	17		T35	3
valid_sources[0x1e]	197383	1			T32	21		T33	6		T37	4337
valid_sources[0x1f]	69639	1			T32	19		T33	14		T37	4213
valid_sources[0x20]	70038	1			T31	12		T32	28		T33	21
valid_sources[0x21]	71282	1			T32	19		T33	10		T35	2
valid_sources[0x22]	74617	1			T31	1		T32	15		T33	10
valid_sources[0x23]	71150	1			T32	24		T33	19		T37	4162
valid_sources[0x24]	79474	1			T32	22		T33	18		T35	1
valid_sources[0x25]	77222	1			T32	32		T33	18		T35	2
valid_sources[0x26]	69692	1			T32	26		T33	14		T35	1
valid_sources[0x27]	72537	1			T32	18		T33	10		T34	478
valid_sources[0x28]	76380	1			T32	10		T33	17		T37	4042
valid_sources[0x29]	77569	1			T31	3		T32	27		T33	15
valid_sources[0x2a]	80005	1			T32	24		T33	19		T37	4088
valid_sources[0x2b]	76565	1			T32	18		T33	11		T35	2
valid_sources[0x2c]	72430	1			T32	19		T33	18		T35	1
valid_sources[0x2d]	71365	1			T31	14		T32	24		T33	9
valid_sources[0x2e]	75476	1			T32	31		T33	13		T35	1
valid_sources[0x2f]	70823	1			T32	15		T33	14		T35	3
valid_sources[0x30]	71990	1			T32	26		T33	18		T35	1
valid_sources[0x31]	70008	1			T32	29		T33	17		T36	11
valid_sources[0x32]	74378	1			T32	21		T33	15		T37	4185
valid_sources[0x33]	143090	1			T32	25		T33	12		T35	1
valid_sources[0x34]	68917	1			T32	27		T33	22		T37	4240
valid_sources[0x35]	72274	1			T32	23		T33	9		T35	1
valid_sources[0x36]	150063	1			T31	3		T32	16		T33	25
valid_sources[0x37]	74320	1			T32	25		T33	19		T37	4085
valid_sources[0x38]	76820	1			T32	19		T33	14		T35	2
valid_sources[0x39]	74405	1			T32	20		T33	32		T37	4309
valid_sources[0x3a]	78296	1			T31	3		T32	21		T33	17
valid_sources[0x3b]	70857	1			T32	27		T33	21		T37	4111
valid_sources[0x3c]	69244	1			T32	13		T33	21		T37	4284
valid_sources[0x3d]	72128	1			T32	19		T33	11		T35	2
valid_sources[0x3e]	72869	1			T32	26		T33	17		T37	4157
valid_sources[0x3f]	91746	1			T32	31		T33	17		T35	1
valid_sources[0x40]	70560	1			T32	21		T33	12		T37	4180
valid_sources[0x41]	73120	1			T32	32		T33	8		T35	1
valid_sources[0x42]	69239	1			T30	27		T32	13		T33	15
valid_sources[0x43]	75938	1			T32	12		T33	15		T35	1
valid_sources[0x44]	71086	1			T32	24		T33	19		T35	2
valid_sources[0x45]	74228	1			T32	18		T33	16		T37	4127
valid_sources[0x46]	71717	1			T32	27		T33	12		T37	4207
valid_sources[0x47]	71540	1			T32	23		T33	28		T35	1
valid_sources[0x48]	72812	1			T32	17		T33	11		T35	3
valid_sources[0x49]	71071	1			T31	1		T32	17		T33	14
valid_sources[0x4a]	71226	1			T32	25		T33	19		T37	4158
valid_sources[0x4b]	72267	1			T32	31		T33	16		T35	1
valid_sources[0x4c]	68754	1			T32	22		T33	11		T35	3
valid_sources[0x4d]	73313	1			T32	20		T33	13		T35	1
valid_sources[0x4e]	69654	1			T32	24		T33	22		T37	4141
valid_sources[0x4f]	72410	1			T32	13		T33	13		T35	1
valid_sources[0x50]	71634	1			T31	2		T32	16		T33	12
valid_sources[0x51]	72805	1			T32	27		T33	19		T35	4
valid_sources[0x52]	74289	1			T32	28		T33	19		T37	4111
valid_sources[0x53]	70024	1			T32	26		T33	21		T35	1
valid_sources[0x54]	67898	1			T32	29		T33	16		T37	4239
valid_sources[0x55]	76906	1			T32	19		T33	9		T35	3
valid_sources[0x56]	68350	1			T32	18		T33	12		T35	2
valid_sources[0x57]	72523	1			T32	30		T33	12		T35	4
valid_sources[0x58]	72884	1			T32	22		T33	15		T37	4229
valid_sources[0x59]	71060	1			T32	22		T33	18		T35	2
valid_sources[0x5a]	85026	1			T32	21		T33	18		T35	1
valid_sources[0x5b]	70661	1			T31	1		T32	23		T33	16
valid_sources[0x5c]	76908	1			T32	25		T33	15		T35	1
valid_sources[0x5d]	76460	1			T32	26		T33	11		T37	4208
valid_sources[0x5e]	79794	1			T32	21		T33	9		T37	4101
valid_sources[0x5f]	76337	1			T32	34		T33	16		T37	4181
valid_sources[0x60]	70416	1			T32	25		T33	17		T35	1
valid_sources[0x61]	80193	1			T32	19		T33	20		T35	4
valid_sources[0x62]	73412	1			T32	16		T33	17		T37	4113
valid_sources[0x63]	71188	1			T32	28		T33	18		T35	1
valid_sources[0x64]	138840	1			T32	15		T33	10		T35	2
valid_sources[0x65]	74375	1			T32	19		T33	14		T35	2
valid_sources[0x66]	71841	1			T32	16		T33	22		T37	4179
valid_sources[0x67]	75905	1			T31	13		T32	22		T33	24
valid_sources[0x68]	70759	1			T31	1		T32	22		T33	15
valid_sources[0x69]	71136	1			T32	26		T33	10		T37	4125
valid_sources[0x6a]	73715	1			T32	14		T33	21		T35	1
valid_sources[0x6b]	70970	1			T32	19		T33	12		T37	4253
valid_sources[0x6c]	71838	1			T32	22		T33	14		T37	4201
valid_sources[0x6d]	75426	1			T32	27		T33	26		T37	4122
valid_sources[0x6e]	78237	1			T32	22		T33	13		T37	4122
valid_sources[0x6f]	70869	1			T32	21		T33	17		T35	7
valid_sources[0x70]	72581	1			T32	18		T33	24		T37	4139
valid_sources[0x71]	76321	1			T32	24		T33	15		T35	1
valid_sources[0x72]	72142	1			T32	27		T33	24		T37	4223
valid_sources[0x73]	75570	1			T32	16		T33	14		T35	1
valid_sources[0x74]	69836	1			T32	20		T33	12		T35	1
valid_sources[0x75]	72799	1			T32	18		T33	10		T35	2
valid_sources[0x76]	73281	1			T32	17		T33	19		T35	2
valid_sources[0x77]	69397	1			T32	22		T33	20		T35	1
valid_sources[0x78]	72339	1			T31	1		T32	17		T33	17
valid_sources[0x79]	74484	1			T32	15		T33	20		T37	4149
valid_sources[0x7a]	78831	1			T32	17		T33	13		T35	1
valid_sources[0x7b]	72399	1			T32	21		T33	13		T37	4072
valid_sources[0x7c]	69249	1			T32	13		T33	21		T35	1
valid_sources[0x7d]	74634	1			T32	19		T33	12		T37	4193
valid_sources[0x7e]	175887	1			T32	26		T33	17		T37	4100
valid_sources[0x7f]	79382	1			T32	27		T33	13		T37	4174
valid_sources[0x80]	69593	1			T32	20		T33	12		T35	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4593192

1

T30

1

T31

94

T32

2408

values[0x0]

all_enables

biggest_size

5903734

1

T30

2

T31

37

T32

353

values[0x1]

all_enables

biggest_size

5907157

1

T30

4

T31

41

T32

356