Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160124991	0	0	0
ctrl_en_input_filter_rd_A	160124991	72384	0	0
intr_ctrl_en_falling_rd_A	160124991	74164	0	0
intr_ctrl_en_lvlhigh_rd_A	160124991	73276	0	0
intr_ctrl_en_lvllow_rd_A	160124991	74797	0	0
intr_ctrl_en_rising_rd_A	160124991	72241	0	0
intr_enable_rd_A	160124991	72961	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	72384	0	0
T1	33339	196	0	0
T2	0	1799	0	0
T3	0	166	0	0
T4	0	3869	0	0
T5	0	325	0	0
T6	0	17145	0	0
T7	0	83	0	0
T8	0	207	0	0
T9	0	3463	0	0
T10	0	2457	0	0
T11	114126	0	0	0
T12	3408	0	0	0
T13	1722	0	0	0
T14	1000	0	0	0
T15	2819	0	0	0
T16	1004	0	0	0
T17	751439	0	0	0
T18	1349	0	0	0
T19	7251	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	74164	0	0
T1	0	152	0	0
T2	0	1667	0	0
T3	0	196	0	0
T4	0	3761	0	0
T5	0	383	0	0
T6	0	18013	0	0
T7	0	71	0	0
T8	0	243	0	0
T9	0	2800	0	0
T20	8647	2	0	0
T21	3147	0	0	0
T22	2309	0	0	0
T23	2131	0	0	0
T24	35071	0	0	0
T25	304867	0	0	0
T26	5883	0	0	0
T27	5264	0	0	0
T28	5060	0	0	0
T29	3140	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	73276	0	0
T1	33339	169	0	0
T2	0	1820	0	0
T3	0	145	0	0
T4	0	4193	0	0
T5	0	338	0	0
T6	0	17764	0	0
T7	0	117	0	0
T8	0	200	0	0
T9	0	3446	0	0
T10	0	2308	0	0
T11	114126	0	0	0
T12	3408	0	0	0
T13	1722	0	0	0
T14	1000	0	0	0
T15	2819	0	0	0
T16	1004	0	0	0
T17	751439	0	0	0
T18	1349	0	0	0
T19	7251	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	74797	0	0
T1	33339	152	0	0
T2	0	1867	0	0
T3	0	178	0	0
T4	0	3960	0	0
T5	0	465	0	0
T6	0	17966	0	0
T7	0	106	0	0
T8	0	232	0	0
T9	0	3289	0	0
T10	0	2303	0	0
T11	114126	0	0	0
T12	3408	0	0	0
T13	1722	0	0	0
T14	1000	0	0	0
T15	2819	0	0	0
T16	1004	0	0	0
T17	751439	0	0	0
T18	1349	0	0	0
T19	7251	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	72241	0	0
T1	0	196	0	0
T2	0	1592	0	0
T3	0	191	0	0
T4	0	3596	0	0
T5	0	442	0	0
T6	0	17415	0	0
T7	0	64	0	0
T8	0	272	0	0
T9	0	3108	0	0
T20	8647	5	0	0
T21	3147	0	0	0
T22	2309	0	0	0
T23	2131	0	0	0
T24	35071	0	0	0
T25	304867	0	0	0
T26	5883	0	0	0
T27	5264	0	0	0
T28	5060	0	0	0
T29	3140	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160124991	72961	0	0
T1	0	161	0	0
T2	0	1789	0	0
T3	0	170	0	0
T4	0	4189	0	0
T5	0	346	0	0
T6	0	17956	0	0
T7	0	75	0	0
T8	0	228	0	0
T9	0	3130	0	0
T20	8647	2	0	0
T21	3147	0	0	0
T22	2309	0	0	0
T23	2131	0	0	0
T24	35071	0	0	0
T25	304867	0	0	0
T26	5883	0	0	0
T27	5264	0	0	0
T28	5060	0	0	0
T29	3140	0	0	0