Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4197997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18868038

1

T28

87

T29

510

T30

19783

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9190796	1			T28	53		T29	826		T30	11054
values[0x0]	6818877	1			T28	27		T29	57		T30	7115
values[0x1]	7056362	1			T28	32		T29	56		T30	7088

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3222107	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19843928

1

T28

94

T29

604

T30

20932

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	80686	1			T28	1		T29	23		T31	2
valid_sources[0x01]	84583	1			T32	7		T34	1		T37	2
valid_sources[0x02]	90164	1			T31	2		T32	16		T34	2
valid_sources[0x03]	81268	1			T31	1		T32	11		T34	1
valid_sources[0x04]	75960	1			T28	1		T32	10		T67	3
valid_sources[0x05]	87440	1			T31	1		T32	5		T33	10
valid_sources[0x06]	78256	1			T28	1		T31	2		T32	5
valid_sources[0x07]	93328	1			T29	6		T32	13		T33	3
valid_sources[0x08]	81065	1			T31	1		T32	4		T33	3
valid_sources[0x09]	90969	1			T32	6		T34	4		T36	1
valid_sources[0x0a]	83824	1			T32	14		T33	5		T34	6
valid_sources[0x0b]	82830	1			T29	17		T31	2		T32	11
valid_sources[0x0c]	82319	1			T31	3		T32	10		T34	1
valid_sources[0x0d]	86404	1			T31	2		T32	12		T33	1
valid_sources[0x0e]	82187	1			T32	13		T33	2		T34	1
valid_sources[0x0f]	84313	1			T32	7		T34	2		T36	1
valid_sources[0x10]	85147	1			T28	1		T31	3		T32	13
valid_sources[0x11]	78316	1			T28	1		T29	19		T31	1
valid_sources[0x12]	84400	1			T28	1		T29	9		T32	6
valid_sources[0x13]	79998	1			T29	40		T32	9		T33	4
valid_sources[0x14]	83735	1			T28	1		T31	3		T32	12
valid_sources[0x15]	100625	1			T29	20		T32	10		T122	1
valid_sources[0x16]	91257	1			T32	12		T33	2		T34	1
valid_sources[0x17]	78125	1			T31	3		T32	8		T34	5
valid_sources[0x18]	89182	1			T31	6		T32	7		T33	5
valid_sources[0x19]	85193	1			T32	9		T34	2		T122	1
valid_sources[0x1a]	164459	1			T32	10		T33	1		T34	2
valid_sources[0x1b]	84974	1			T28	1		T29	95		T32	11
valid_sources[0x1c]	82765	1			T28	1		T31	4		T32	10
valid_sources[0x1d]	90801	1			T29	3		T31	4		T32	6
valid_sources[0x1e]	81082	1			T31	1		T32	12		T122	2
valid_sources[0x1f]	86145	1			T28	1		T31	2		T32	9
valid_sources[0x20]	84124	1			T31	7		T32	9		T33	12
valid_sources[0x21]	87833	1			T28	1		T32	13		T34	2
valid_sources[0x22]	90786	1			T29	9		T31	2		T32	9
valid_sources[0x23]	82141	1			T31	3		T32	7		T33	2
valid_sources[0x24]	83442	1			T29	2		T32	17		T34	1
valid_sources[0x25]	85332	1			T28	1		T32	4		T33	3
valid_sources[0x26]	80769	1			T28	1		T31	4		T32	13
valid_sources[0x27]	79146	1			T32	13		T33	4		T34	1
valid_sources[0x28]	94801	1			T28	1		T31	1		T32	10
valid_sources[0x29]	88877	1			T29	5		T32	6		T34	5
valid_sources[0x2a]	84577	1			T31	4		T32	7		T33	4
valid_sources[0x2b]	86929	1			T28	2		T32	11		T33	3
valid_sources[0x2c]	83270	1			T31	6		T32	8		T33	3
valid_sources[0x2d]	84897	1			T29	50		T31	2		T32	9
valid_sources[0x2e]	90537	1			T32	8		T33	1		T34	2
valid_sources[0x2f]	90245	1			T32	13		T33	2		T35	3360
valid_sources[0x30]	90976	1			T28	4		T29	1		T31	1
valid_sources[0x31]	75419	1			T28	1		T31	3		T32	7
valid_sources[0x32]	159305	1			T28	1		T29	9		T32	10
valid_sources[0x33]	95276	1			T31	4		T32	8		T33	6
valid_sources[0x34]	91750	1			T31	1		T32	12		T34	3
valid_sources[0x35]	85772	1			T29	4		T32	9		T33	1
valid_sources[0x36]	79022	1			T31	2		T32	10		T34	2
valid_sources[0x37]	86751	1			T31	1		T32	6		T33	3
valid_sources[0x38]	188889	1			T28	1		T31	4		T32	9
valid_sources[0x39]	92195	1			T32	16		T33	2		T34	2
valid_sources[0x3a]	98659	1			T31	3		T32	3		T33	6
valid_sources[0x3b]	137005	1			T28	1		T31	2		T32	5
valid_sources[0x3c]	93255	1			T31	1		T32	6		T33	1
valid_sources[0x3d]	86039	1			T31	1		T32	12		T33	6
valid_sources[0x3e]	84657	1			T31	3		T32	13		T33	1
valid_sources[0x3f]	86430	1			T28	1		T32	14		T33	2
valid_sources[0x40]	88343	1			T32	6		T33	8		T34	3
valid_sources[0x41]	95902	1			T29	13		T31	2		T32	7
valid_sources[0x42]	149914	1			T31	3		T32	9		T33	2
valid_sources[0x43]	89340	1			T28	1		T31	2		T32	5
valid_sources[0x44]	92574	1			T28	1		T29	1		T32	15
valid_sources[0x45]	85173	1			T28	1		T32	8		T67	1
valid_sources[0x46]	85668	1			T29	42		T31	2		T32	7
valid_sources[0x47]	85410	1			T31	1		T32	12		T33	4
valid_sources[0x48]	84647	1			T28	1		T31	2		T32	6
valid_sources[0x49]	83900	1			T28	1		T32	11		T34	2
valid_sources[0x4a]	78538	1			T29	19		T31	3		T32	19
valid_sources[0x4b]	89892	1			T32	13		T34	1		T37	1
valid_sources[0x4c]	120707	1			T28	1		T31	5		T32	13
valid_sources[0x4d]	82150	1			T31	5		T32	14		T34	2
valid_sources[0x4e]	84448	1			T28	2		T31	1		T32	9
valid_sources[0x4f]	78303	1			T28	1		T31	1		T32	10
valid_sources[0x50]	90333	1			T31	1		T32	10		T33	1
valid_sources[0x51]	79882	1			T28	1		T32	13		T33	2
valid_sources[0x52]	87448	1			T28	1		T31	8		T32	9
valid_sources[0x53]	80616	1			T28	1		T31	3		T32	7
valid_sources[0x54]	82053	1			T28	1		T31	3		T32	6
valid_sources[0x55]	81763	1			T28	1		T31	6		T32	9
valid_sources[0x56]	91130	1			T28	1		T31	1		T32	6
valid_sources[0x57]	83731	1			T32	13		T33	1		T68	2
valid_sources[0x58]	87330	1			T31	1		T32	7		T34	1
valid_sources[0x59]	94869	1			T28	1		T29	11		T31	2
valid_sources[0x5a]	84292	1			T28	1		T32	6		T36	1
valid_sources[0x5b]	79705	1			T28	1		T29	4		T31	4
valid_sources[0x5c]	80559	1			T28	1		T29	33		T31	4
valid_sources[0x5d]	81257	1			T29	3		T31	3		T32	13
valid_sources[0x5e]	77819	1			T31	3		T32	5		T34	7
valid_sources[0x5f]	85999	1			T31	3		T32	10		T33	3
valid_sources[0x60]	129686	1			T29	11		T32	9		T33	7
valid_sources[0x61]	84365	1			T29	8		T31	3		T32	8
valid_sources[0x62]	82792	1			T32	15		T33	5		T34	2
valid_sources[0x63]	84695	1			T28	1		T31	5		T32	7
valid_sources[0x64]	81901	1			T28	1		T32	9		T33	9
valid_sources[0x65]	81986	1			T31	2		T32	14		T34	7
valid_sources[0x66]	84183	1			T32	11		T34	5		T36	6
valid_sources[0x67]	86747	1			T29	36		T31	1		T32	6
valid_sources[0x68]	85120	1			T28	2		T31	3		T32	12
valid_sources[0x69]	87970	1			T31	3		T32	7		T122	1
valid_sources[0x6a]	86857	1			T28	1		T31	1		T32	10
valid_sources[0x6b]	88384	1			T29	40		T32	7		T34	2
valid_sources[0x6c]	89236	1			T31	1		T32	8		T33	1
valid_sources[0x6d]	85476	1			T32	8		T34	3		T37	1
valid_sources[0x6e]	98138	1			T31	5		T32	11		T37	1
valid_sources[0x6f]	82695	1			T28	1		T31	2		T32	6
valid_sources[0x70]	84687	1			T28	1		T29	28		T31	1
valid_sources[0x71]	81847	1			T32	8		T33	5		T34	2
valid_sources[0x72]	84989	1			T31	2		T32	8		T33	3
valid_sources[0x73]	79594	1			T29	7		T31	3		T32	8
valid_sources[0x74]	87884	1			T31	5		T32	10		T34	2
valid_sources[0x75]	89619	1			T28	2		T31	2		T32	12
valid_sources[0x76]	80576	1			T31	1		T32	7		T33	4
valid_sources[0x77]	78408	1			T31	3		T32	7		T34	6
valid_sources[0x78]	84692	1			T32	14		T37	9		T67	3
valid_sources[0x79]	82254	1			T28	1		T29	17		T31	2
valid_sources[0x7a]	86289	1			T31	1		T32	15		T33	5
valid_sources[0x7b]	89699	1			T31	2		T32	12		T34	2
valid_sources[0x7c]	86120	1			T28	1		T32	10		T34	3
valid_sources[0x7d]	84596	1			T31	4		T32	9		T33	4
valid_sources[0x7e]	135644	1			T31	2		T32	14		T34	5
valid_sources[0x7f]	86750	1			T29	22		T31	4		T32	5
valid_sources[0x80]	86972	1			T31	8		T32	10		T33	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5283672

1

T28

28

T29

397

T30

5580

values[0x0]

all_enables

biggest_size

6794804

1

T28

27

T29

57

T30

7115

values[0x1]

all_enables

biggest_size

6789562

1

T28

32

T29

56

T30

7088