Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	182438095	0	0	0
ctrl_en_input_filter_rd_A	182438095	96921	0	0
intr_ctrl_en_falling_rd_A	182438095	101414	0	0
intr_ctrl_en_lvlhigh_rd_A	182438095	98390	0	0
intr_ctrl_en_lvllow_rd_A	182438095	100836	0	0
intr_ctrl_en_rising_rd_A	182438095	96345	0	0
intr_enable_rd_A	182438095	97392	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	96921	0	0
T1	4183	9	0	0
T2	0	25	0	0
T3	0	4300	0	0
T4	0	376	0	0
T5	0	2014	0	0
T6	0	143	0	0
T7	0	17582	0	0
T8	0	128	0	0
T9	0	4812	0	0
T10	0	2447	0	0
T11	4609	0	0	0
T12	1085	0	0	0
T13	2844	0	0	0
T14	3572	0	0	0
T15	9251	0	0	0
T16	40852	0	0	0
T17	4064	0	0	0
T18	5851	0	0	0
T19	2885	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	101414	0	0
T1	4183	8	0	0
T2	0	51	0	0
T3	0	4559	0	0
T4	0	382	0	0
T5	0	2020	0	0
T6	0	146	0	0
T7	0	19222	0	0
T8	0	93	0	0
T9	0	4844	0	0
T10	0	2463	0	0
T11	4609	0	0	0
T12	1085	0	0	0
T13	2844	0	0	0
T14	3572	0	0	0
T15	9251	0	0	0
T16	40852	0	0	0
T17	4064	0	0	0
T18	5851	0	0	0
T19	2885	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	98390	0	0
T2	10218	31	0	0
T3	126278	4434	0	0
T4	55754	408	0	0
T5	0	2102	0	0
T6	0	154	0	0
T7	0	17415	0	0
T8	0	50	0	0
T9	0	4914	0	0
T10	0	2377	0	0
T20	0	4057	0	0
T21	1414	0	0	0
T22	2776	0	0	0
T23	1923	0	0	0
T24	6356	0	0	0
T25	11104	0	0	0
T26	3150	0	0	0
T27	4661	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	100836	0	0
T2	10218	56	0	0
T3	126278	4474	0	0
T4	55754	322	0	0
T5	0	2075	0	0
T6	0	156	0	0
T7	0	19074	0	0
T8	0	114	0	0
T9	0	4676	0	0
T10	0	2686	0	0
T20	0	3847	0	0
T21	1414	0	0	0
T22	2776	0	0	0
T23	1923	0	0	0
T24	6356	0	0	0
T25	11104	0	0	0
T26	3150	0	0	0
T27	4661	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	96345	0	0
T1	4183	3	0	0
T2	0	57	0	0
T3	0	4555	0	0
T4	0	325	0	0
T5	0	2087	0	0
T6	0	119	0	0
T7	0	17457	0	0
T8	0	101	0	0
T9	0	4744	0	0
T10	0	2513	0	0
T11	4609	0	0	0
T12	1085	0	0	0
T13	2844	0	0	0
T14	3572	0	0	0
T15	9251	0	0	0
T16	40852	0	0	0
T17	4064	0	0	0
T18	5851	0	0	0
T19	2885	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182438095	97392	0	0
T1	4183	6	0	0
T2	0	33	0	0
T3	0	4212	0	0
T4	0	362	0	0
T5	0	2161	0	0
T6	0	150	0	0
T7	0	17458	0	0
T8	0	114	0	0
T9	0	4627	0	0
T10	0	2473	0	0
T11	4609	0	0	0
T12	1085	0	0	0
T13	2844	0	0	0
T14	3572	0	0	0
T15	9251	0	0	0
T16	40852	0	0	0
T17	4064	0	0	0
T18	5851	0	0	0
T19	2885	0	0	0