Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3628670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15820445

1

T1

10295

T11

373

T12

164

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7865529	1			T1	5187		T11	93		T12	95
values[0x0]	5699580	1			T1	3915		T11	168		T12	47
values[0x1]	5884006	1			T1	3783		T11	160		T12	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2801157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16647958

1

T1

10799

T11

380

T12

170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	69778	1			T1	45		T12	6		T13	15
valid_sources[0x01]	72931	1			T1	65		T13	3		T14	505
valid_sources[0x02]	67453	1			T1	47		T13	7		T14	592
valid_sources[0x03]	73049	1			T1	31		T13	5		T14	525
valid_sources[0x04]	66563	1			T1	52		T12	3		T13	2
valid_sources[0x05]	71522	1			T1	45		T13	3		T14	575
valid_sources[0x06]	66557	1			T1	49		T13	8		T14	486
valid_sources[0x07]	77199	1			T1	56		T13	3		T14	476
valid_sources[0x08]	70546	1			T1	53		T12	2		T13	1
valid_sources[0x09]	72340	1			T1	63		T13	6		T14	604
valid_sources[0x0a]	75483	1			T1	54		T13	7		T14	514
valid_sources[0x0b]	72387	1			T1	45		T13	6		T14	457
valid_sources[0x0c]	69393	1			T1	41		T12	3		T13	18
valid_sources[0x0d]	67978	1			T1	48		T12	2		T13	1
valid_sources[0x0e]	77075	1			T1	52		T13	3		T14	446
valid_sources[0x0f]	115807	1			T1	42		T12	2		T13	5
valid_sources[0x10]	79765	1			T1	69		T12	2		T13	4
valid_sources[0x11]	74364	1			T1	56		T12	1		T13	10
valid_sources[0x12]	75720	1			T1	50		T13	13		T14	478
valid_sources[0x13]	69502	1			T1	47		T13	3		T14	496
valid_sources[0x14]	66507	1			T1	55		T14	594		T17	3
valid_sources[0x15]	76552	1			T1	57		T13	1		T14	586
valid_sources[0x16]	67731	1			T1	45		T13	4		T14	496
valid_sources[0x17]	67145	1			T1	54		T14	546		T23	1
valid_sources[0x18]	67194	1			T1	45		T13	9		T14	504
valid_sources[0x19]	69767	1			T1	58		T13	9		T14	508
valid_sources[0x1a]	72399	1			T1	47		T11	421		T12	3
valid_sources[0x1b]	73209	1			T1	51		T12	1		T13	18
valid_sources[0x1c]	72615	1			T1	37		T13	3		T14	533
valid_sources[0x1d]	72565	1			T1	60		T13	4		T14	513
valid_sources[0x1e]	72320	1			T1	48		T14	494		T110	2
valid_sources[0x1f]	67536	1			T1	45		T14	532		T17	1
valid_sources[0x20]	71753	1			T1	55		T13	4		T14	463
valid_sources[0x21]	73897	1			T1	59		T13	2		T14	488
valid_sources[0x22]	68309	1			T1	64		T14	444		T17	2
valid_sources[0x23]	70344	1			T1	62		T14	439		T23	3
valid_sources[0x24]	66894	1			T1	54		T13	9		T14	526
valid_sources[0x25]	66895	1			T1	56		T13	7		T14	507
valid_sources[0x26]	75085	1			T1	55		T12	5		T14	572
valid_sources[0x27]	119707	1			T1	59		T13	1		T14	557
valid_sources[0x28]	71050	1			T1	43		T13	6		T14	533
valid_sources[0x29]	68016	1			T1	54		T13	4		T14	442
valid_sources[0x2a]	72979	1			T1	60		T13	14		T14	471
valid_sources[0x2b]	68732	1			T1	48		T13	3		T14	502
valid_sources[0x2c]	72476	1			T1	65		T13	3		T14	548
valid_sources[0x2d]	74495	1			T1	37		T13	3		T14	534
valid_sources[0x2e]	77233	1			T1	34		T12	3		T13	14
valid_sources[0x2f]	74117	1			T1	56		T13	16		T14	487
valid_sources[0x30]	76932	1			T1	43		T12	2		T13	3
valid_sources[0x31]	69551	1			T1	53		T12	2		T13	8
valid_sources[0x32]	78001	1			T1	44		T12	1		T14	493
valid_sources[0x33]	71572	1			T1	46		T13	7		T14	549
valid_sources[0x34]	70725	1			T1	55		T12	3		T13	2
valid_sources[0x35]	78504	1			T1	54		T12	1		T13	1
valid_sources[0x36]	77055	1			T1	67		T13	8		T14	530
valid_sources[0x37]	73143	1			T1	46		T13	7		T14	504
valid_sources[0x38]	72064	1			T1	38		T13	2		T14	486
valid_sources[0x39]	72430	1			T1	43		T13	5		T14	428
valid_sources[0x3a]	68421	1			T1	38		T13	3		T14	509
valid_sources[0x3b]	78440	1			T1	52		T13	10		T14	440
valid_sources[0x3c]	74798	1			T1	39		T13	1		T14	549
valid_sources[0x3d]	74091	1			T1	57		T12	1		T13	1
valid_sources[0x3e]	78040	1			T1	51		T12	1		T14	571
valid_sources[0x3f]	69211	1			T1	51		T12	1		T13	5
valid_sources[0x40]	69645	1			T1	34		T14	509		T17	2
valid_sources[0x41]	71260	1			T1	56		T14	413		T23	1
valid_sources[0x42]	75919	1			T1	59		T13	6		T14	544
valid_sources[0x43]	74015	1			T1	53		T13	2		T14	462
valid_sources[0x44]	73143	1			T1	39		T13	5		T14	390
valid_sources[0x45]	118860	1			T1	49		T13	6		T14	451
valid_sources[0x46]	70128	1			T1	61		T13	9		T14	507
valid_sources[0x47]	72875	1			T1	50		T13	4		T14	460
valid_sources[0x48]	75591	1			T1	45		T13	2		T14	511
valid_sources[0x49]	69270	1			T1	54		T12	2		T13	1
valid_sources[0x4a]	72231	1			T1	46		T14	511		T15	1
valid_sources[0x4b]	64430	1			T1	55		T12	7		T13	15
valid_sources[0x4c]	211326	1			T1	41		T14	480		T23	3
valid_sources[0x4d]	71900	1			T1	52		T13	4		T14	621
valid_sources[0x4e]	73393	1			T1	48		T13	9		T14	498
valid_sources[0x4f]	78951	1			T1	42		T12	5		T14	439
valid_sources[0x50]	73490	1			T1	62		T12	1		T13	4
valid_sources[0x51]	77075	1			T1	48		T14	545		T23	1
valid_sources[0x52]	72573	1			T1	40		T12	4		T13	6
valid_sources[0x53]	67204	1			T1	55		T13	3		T14	513
valid_sources[0x54]	71186	1			T1	57		T13	3		T14	527
valid_sources[0x55]	76913	1			T1	53		T13	6		T14	541
valid_sources[0x56]	75833	1			T1	59		T12	5		T13	1
valid_sources[0x57]	73176	1			T1	50		T13	7		T14	548
valid_sources[0x58]	70951	1			T1	36		T12	1		T13	3
valid_sources[0x59]	78506	1			T1	53		T13	4		T14	440
valid_sources[0x5a]	193632	1			T1	55		T12	1		T13	10
valid_sources[0x5b]	72514	1			T1	57		T12	5		T14	578
valid_sources[0x5c]	84807	1			T1	58		T12	3		T13	10
valid_sources[0x5d]	71778	1			T1	51		T14	599		T19	6
valid_sources[0x5e]	169785	1			T1	57		T12	1		T14	498
valid_sources[0x5f]	66068	1			T1	32		T13	5		T14	495
valid_sources[0x60]	82058	1			T1	49		T13	8		T14	534
valid_sources[0x61]	71176	1			T1	45		T12	1		T13	19
valid_sources[0x62]	72421	1			T1	61		T13	2		T14	559
valid_sources[0x63]	67000	1			T1	40		T13	4		T14	438
valid_sources[0x64]	72875	1			T1	52		T13	3		T14	456
valid_sources[0x65]	69471	1			T1	47		T13	2		T14	497
valid_sources[0x66]	79018	1			T1	51		T14	531		T19	2
valid_sources[0x67]	83251	1			T1	48		T12	1		T13	1
valid_sources[0x68]	68576	1			T1	50		T14	499		T17	1
valid_sources[0x69]	67665	1			T1	49		T13	2		T14	525
valid_sources[0x6a]	66718	1			T1	44		T14	510		T110	3
valid_sources[0x6b]	73024	1			T1	62		T13	4		T14	492
valid_sources[0x6c]	67134	1			T1	60		T12	1		T13	5
valid_sources[0x6d]	81107	1			T1	43		T13	10		T14	507
valid_sources[0x6e]	74879	1			T1	59		T13	3		T14	513
valid_sources[0x6f]	66084	1			T1	42		T13	1		T14	502
valid_sources[0x70]	72796	1			T1	50		T12	3		T13	2
valid_sources[0x71]	68697	1			T1	55		T13	5		T14	503
valid_sources[0x72]	72214	1			T1	62		T12	2		T13	7
valid_sources[0x73]	72124	1			T1	56		T13	3		T14	379
valid_sources[0x74]	68942	1			T1	63		T13	6		T14	503
valid_sources[0x75]	73555	1			T1	36		T13	7		T14	581
valid_sources[0x76]	75480	1			T1	59		T13	1		T14	536
valid_sources[0x77]	75164	1			T1	59		T13	4		T14	546
valid_sources[0x78]	70111	1			T1	52		T12	1		T13	6
valid_sources[0x79]	76424	1			T1	46		T12	2		T13	2
valid_sources[0x7a]	159754	1			T1	40		T13	3		T14	532
valid_sources[0x7b]	72517	1			T1	37		T13	2		T14	510
valid_sources[0x7c]	68517	1			T1	43		T12	1		T14	466
valid_sources[0x7d]	69608	1			T1	41		T13	4		T14	513
valid_sources[0x7e]	69934	1			T1	62		T12	1		T13	11
valid_sources[0x7f]	61771	1			T1	49		T13	14		T14	406
valid_sources[0x80]	73243	1			T1	64		T13	5		T14	446

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4455901

1

T1

2597

T11

45

T12

50

values[0x0]

all_enables

biggest_size

5680995

1

T1

3915

T11

168

T12

47

values[0x1]

all_enables

biggest_size

5683549

1

T1

3783

T11

160

T12

67