Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	146657322	0	0	0
ctrl_en_input_filter_rd_A	146657322	53990	0	0
intr_ctrl_en_falling_rd_A	146657322	53508	0	0
intr_ctrl_en_lvlhigh_rd_A	146657322	53800	0	0
intr_ctrl_en_lvllow_rd_A	146657322	53423	0	0
intr_ctrl_en_rising_rd_A	146657322	53324	0	0
intr_enable_rd_A	146657322	52929	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	53990	0	0
T1	203444	199	0	0
T2	0	1223	0	0
T3	0	1047	0	0
T4	0	439	0	0
T5	0	6	0	0
T6	0	7391	0	0
T7	0	2989	0	0
T8	0	135	0	0
T9	0	4	0	0
T10	0	1330	0	0
T11	2508	0	0	0
T12	3377	0	0	0
T13	4844	0	0	0
T14	127185	0	0	0
T15	1219	0	0	0
T16	2018	0	0	0
T17	3983	0	0	0
T18	9381	0	0	0
T19	5888	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	53508	0	0
T1	203444	201	0	0
T2	0	1523	0	0
T3	0	1029	0	0
T4	0	363	0	0
T5	0	7	0	0
T6	0	7467	0	0
T7	0	2966	0	0
T8	0	131	0	0
T10	0	1273	0	0
T11	2508	0	0	0
T12	3377	0	0	0
T13	4844	0	0	0
T14	127185	0	0	0
T15	1219	0	0	0
T16	2018	0	0	0
T17	3983	0	0	0
T18	9381	0	0	0
T19	5888	0	0	0
T20	0	2	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	53800	0	0
T1	203444	164	0	0
T2	0	1274	0	0
T3	0	1063	0	0
T4	0	403	0	0
T6	0	7404	0	0
T7	0	3080	0	0
T8	0	157	0	0
T10	0	1236	0	0
T11	2508	0	0	0
T12	3377	0	0	0
T13	4844	0	0	0
T14	127185	0	0	0
T15	1219	0	0	0
T16	2018	0	0	0
T17	3983	0	0	0
T18	9381	0	0	0
T19	5888	0	0	0
T21	0	6	0	0
T22	0	2	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	53423	0	0
T1	203444	235	0	0
T2	0	1244	0	0
T3	0	909	0	0
T4	0	275	0	0
T5	0	6	0	0
T6	0	7311	0	0
T7	0	2994	0	0
T8	0	151	0	0
T11	2508	0	0	0
T12	3377	0	0	0
T13	4844	0	0	0
T14	127185	0	0	0
T15	1219	0	0	0
T16	2018	0	0	0
T17	3983	0	0	0
T18	9381	0	0	0
T19	5888	0	0	0
T21	0	10	0	0
T22	0	9	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	53324	0	0
T1	203444	181	0	0
T2	0	1248	0	0
T3	0	1045	0	0
T4	0	359	0	0
T6	0	7444	0	0
T7	0	2798	0	0
T8	0	97	0	0
T10	0	1302	0	0
T11	2508	0	0	0
T12	3377	0	0	0
T13	4844	0	0	0
T14	127185	0	0	0
T15	1219	0	0	0
T16	2018	0	0	0
T17	3983	0	0	0
T18	9381	0	0	0
T19	5888	0	0	0
T21	0	5	0	0
T22	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146657322	52929	0	0
T1	203444	256	0	0
T2	0	1023	0	0
T3	0	1021	0	0
T4	0	273	0	0
T5	0	6	0	0
T6	0	7167	0	0
T7	0	2857	0	0
T8	0	147	0	0
T10	0	1307	0	0
T11	2508	0	0	0
T12	3377	0	0	0
T13	4844	0	0	0
T14	127185	0	0	0
T15	1219	0	0	0
T16	2018	0	0	0
T17	3983	0	0	0
T18	9381	0	0	0
T19	5888	0	0	0
T21	0	3	0	0