Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3714710	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16094909

1

T24

363

T1

8905

T11

195

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8021996	1			T24	83		T25	1		T1	4636
values[0x0]	5802457	1			T24	176		T1	3289		T11	87
values[0x1]	5985166	1			T24	148		T1	3272		T11	77

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2868943	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

16940676

1

T24

371

T1

9353

T11

199

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	77083	1			T1	34		T11	1		T2	167
valid_sources[0x01]	141654	1			T1	50		T2	109		T13	2236
valid_sources[0x02]	73020	1			T1	64		T2	219		T13	2340
valid_sources[0x03]	75576	1			T1	69		T2	100		T13	2343
valid_sources[0x04]	66293	1			T1	27		T11	2		T2	147
valid_sources[0x05]	73570	1			T1	57		T2	177		T13	2325
valid_sources[0x06]	69922	1			T1	44		T2	234		T13	2244
valid_sources[0x07]	74424	1			T1	55		T2	226		T13	2182
valid_sources[0x08]	66824	1			T1	48		T11	4		T2	314
valid_sources[0x09]	81052	1			T1	52		T2	207		T13	2264
valid_sources[0x0a]	80082	1			T1	57		T11	4		T2	202
valid_sources[0x0b]	74632	1			T1	46		T2	177		T13	2204
valid_sources[0x0c]	69471	1			T1	21		T11	1		T2	231
valid_sources[0x0d]	72586	1			T1	11		T11	2		T2	222
valid_sources[0x0e]	73755	1			T1	52		T2	144		T13	2136
valid_sources[0x0f]	65993	1			T1	37		T2	227		T13	2348
valid_sources[0x10]	76155	1			T1	44		T11	4		T2	262
valid_sources[0x11]	75288	1			T1	55		T2	287		T13	2113
valid_sources[0x12]	72334	1			T1	43		T2	245		T13	2290
valid_sources[0x13]	78199	1			T1	49		T11	1		T2	198
valid_sources[0x14]	64709	1			T1	64		T2	153		T13	2203
valid_sources[0x15]	77492	1			T1	29		T11	1		T2	193
valid_sources[0x16]	74768	1			T1	65		T11	1		T2	114
valid_sources[0x17]	67105	1			T1	30		T2	217		T13	2155
valid_sources[0x18]	71251	1			T1	50		T11	1		T2	243
valid_sources[0x19]	80100	1			T1	59		T2	263		T13	2256
valid_sources[0x1a]	78701	1			T1	35		T2	212		T13	2280
valid_sources[0x1b]	69665	1			T1	61		T2	324		T13	2369
valid_sources[0x1c]	70203	1			T1	48		T2	254		T13	2151
valid_sources[0x1d]	69241	1			T1	24		T2	181		T13	2095
valid_sources[0x1e]	69701	1			T1	35		T12	18		T2	180
valid_sources[0x1f]	231315	1			T1	73		T2	146		T13	2166
valid_sources[0x20]	71250	1			T1	22		T2	199		T13	2252
valid_sources[0x21]	71699	1			T1	38		T2	178		T13	2340
valid_sources[0x22]	68390	1			T1	38		T11	3		T2	292
valid_sources[0x23]	83449	1			T1	27		T11	1		T12	20
valid_sources[0x24]	91074	1			T1	49		T11	1		T12	15
valid_sources[0x25]	73070	1			T1	60		T11	4		T2	263
valid_sources[0x26]	72753	1			T1	64		T2	206		T13	2224
valid_sources[0x27]	70409	1			T1	53		T11	2		T2	204
valid_sources[0x28]	71298	1			T1	42		T11	2		T2	213
valid_sources[0x29]	79386	1			T1	81		T11	1		T2	239
valid_sources[0x2a]	70743	1			T1	57		T11	1		T2	176
valid_sources[0x2b]	70598	1			T1	48		T11	1		T2	164
valid_sources[0x2c]	69964	1			T1	53		T2	233		T13	2267
valid_sources[0x2d]	73238	1			T1	25		T2	350		T13	2221
valid_sources[0x2e]	68619	1			T1	34		T2	302		T13	2132
valid_sources[0x2f]	77341	1			T1	41		T2	195		T13	2220
valid_sources[0x30]	73473	1			T1	22		T2	282		T13	2236
valid_sources[0x31]	77949	1			T1	65		T2	235		T13	2189
valid_sources[0x32]	79181	1			T1	37		T2	292		T13	2235
valid_sources[0x33]	77157	1			T1	16		T2	144		T13	2201
valid_sources[0x34]	69961	1			T1	30		T2	229		T13	2251
valid_sources[0x35]	72915	1			T1	47		T11	3		T2	196
valid_sources[0x36]	70977	1			T1	34		T2	200		T13	2161
valid_sources[0x37]	78673	1			T1	64		T2	151		T13	2092
valid_sources[0x38]	80240	1			T1	32		T2	187		T13	2187
valid_sources[0x39]	71305	1			T1	72		T2	243		T13	2209
valid_sources[0x3a]	90264	1			T1	22		T2	225		T13	2158
valid_sources[0x3b]	71841	1			T1	26		T11	3		T2	267
valid_sources[0x3c]	74834	1			T1	39		T2	136		T13	2140
valid_sources[0x3d]	75318	1			T1	32		T11	1		T2	165
valid_sources[0x3e]	75348	1			T1	23		T2	285		T13	2188
valid_sources[0x3f]	73693	1			T1	32		T12	119		T2	274
valid_sources[0x40]	71750	1			T1	48		T11	5		T2	132
valid_sources[0x41]	76059	1			T1	56		T11	2		T2	182
valid_sources[0x42]	64647	1			T1	35		T11	1		T2	194
valid_sources[0x43]	70711	1			T1	32		T11	1		T2	160
valid_sources[0x44]	71331	1			T1	47		T2	217		T13	2310
valid_sources[0x45]	66494	1			T1	36		T2	256		T13	2339
valid_sources[0x46]	69925	1			T1	34		T11	1		T2	154
valid_sources[0x47]	74424	1			T1	25		T2	140		T13	2218
valid_sources[0x48]	72787	1			T1	47		T2	227		T13	2158
valid_sources[0x49]	72678	1			T1	51		T2	199		T13	2106
valid_sources[0x4a]	72902	1			T1	32		T11	5		T2	250
valid_sources[0x4b]	70328	1			T1	51		T11	3		T2	200
valid_sources[0x4c]	67152	1			T1	14		T2	232		T13	2255
valid_sources[0x4d]	74253	1			T1	49		T11	2		T2	192
valid_sources[0x4e]	66530	1			T1	44		T2	226		T13	2256
valid_sources[0x4f]	70984	1			T1	30		T11	2		T2	236
valid_sources[0x50]	70554	1			T1	70		T2	223		T13	2226
valid_sources[0x51]	94983	1			T1	66		T11	4		T2	242
valid_sources[0x52]	72176	1			T1	54		T11	2		T2	220
valid_sources[0x53]	73973	1			T1	45		T2	163		T13	2251
valid_sources[0x54]	65698	1			T1	76		T11	1		T2	284
valid_sources[0x55]	74687	1			T1	25		T11	1		T2	201
valid_sources[0x56]	81366	1			T1	30		T2	253		T13	2210
valid_sources[0x57]	66546	1			T1	44		T2	221		T13	2192
valid_sources[0x58]	69279	1			T1	37		T2	226		T13	2210
valid_sources[0x59]	74667	1			T1	43		T2	262		T13	2252
valid_sources[0x5a]	69639	1			T1	47		T2	213		T13	2172
valid_sources[0x5b]	71388	1			T1	65		T11	3		T2	267
valid_sources[0x5c]	65213	1			T1	44		T2	183		T13	2323
valid_sources[0x5d]	70411	1			T1	35		T2	320		T13	2208
valid_sources[0x5e]	76908	1			T1	83		T2	349		T13	2311
valid_sources[0x5f]	69602	1			T1	61		T2	193		T13	2214
valid_sources[0x60]	74954	1			T1	32		T2	336		T13	2223
valid_sources[0x61]	79899	1			T1	21		T2	120		T13	2172
valid_sources[0x62]	86679	1			T1	55		T11	2		T2	144
valid_sources[0x63]	70199	1			T1	32		T11	2		T2	316
valid_sources[0x64]	69454	1			T1	55		T11	2		T2	257
valid_sources[0x65]	68236	1			T1	66		T2	240		T13	2161
valid_sources[0x66]	69214	1			T1	42		T11	2		T2	272
valid_sources[0x67]	69758	1			T1	72		T11	1		T2	129
valid_sources[0x68]	75766	1			T1	41		T11	1		T2	152
valid_sources[0x69]	73958	1			T1	49		T2	192		T13	2098
valid_sources[0x6a]	75121	1			T1	32		T11	1		T2	162
valid_sources[0x6b]	66677	1			T1	55		T11	1		T2	215
valid_sources[0x6c]	71322	1			T1	48		T11	4		T2	237
valid_sources[0x6d]	67023	1			T1	55		T11	5		T12	18
valid_sources[0x6e]	65562	1			T1	53		T11	1		T2	194
valid_sources[0x6f]	71124	1			T25	1		T1	28		T2	170
valid_sources[0x70]	190303	1			T1	50		T11	2		T2	254
valid_sources[0x71]	206204	1			T1	60		T2	237		T13	2192
valid_sources[0x72]	77251	1			T1	45		T11	2		T2	167
valid_sources[0x73]	68138	1			T1	45		T2	179		T13	2164
valid_sources[0x74]	143457	1			T1	31		T2	261		T13	2132
valid_sources[0x75]	70765	1			T1	43		T2	176		T13	2187
valid_sources[0x76]	75288	1			T1	36		T2	243		T13	2227
valid_sources[0x77]	81006	1			T1	32		T11	6		T2	205
valid_sources[0x78]	79618	1			T1	102		T11	1		T2	264
valid_sources[0x79]	67676	1			T1	34		T11	2		T2	245
valid_sources[0x7a]	76385	1			T1	59		T2	283		T13	2332
valid_sources[0x7b]	81876	1			T1	47		T2	243		T13	2136
valid_sources[0x7c]	69654	1			T1	56		T2	196		T13	2307
valid_sources[0x7d]	77706	1			T1	50		T11	1		T2	204
valid_sources[0x7e]	74929	1			T1	42		T2	235		T13	2304
valid_sources[0x7f]	68199	1			T1	58		T11	2		T2	175
valid_sources[0x80]	71004	1			T1	42		T2	250		T13	2166

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4526954

1

T24

39

T1

2344

T11

31

values[0x0]

all_enables

biggest_size

5783920

1

T24

176

T1

3289

T11

87

values[0x1]

all_enables

biggest_size

5784035

1

T24

148

T1

3272

T11

77