Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	149593465	0	0	0
ctrl_en_input_filter_rd_A	149593465	94915	0	0
intr_ctrl_en_falling_rd_A	149593465	100047	0	0
intr_ctrl_en_lvlhigh_rd_A	149593465	96205	0	0
intr_ctrl_en_lvllow_rd_A	149593465	100083	0	0
intr_ctrl_en_rising_rd_A	149593465	94032	0	0
intr_enable_rd_A	149593465	96217	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	94915	0	0
T1	150449	258	0	0
T2	692529	1237	0	0
T3	0	25574	0	0
T4	0	1	0	0
T5	0	4694	0	0
T6	0	9	0	0
T7	0	703	0	0
T8	0	8	0	0
T9	0	15	0	0
T10	0	90	0	0
T11	3814	0	0	0
T12	3156	0	0	0
T13	318137	0	0	0
T14	249442	0	0	0
T15	1124	0	0	0
T16	4693	0	0	0
T17	2179	0	0	0
T18	4419	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	100047	0	0
T1	150449	225	0	0
T2	692529	1353	0	0
T3	0	27930	0	0
T5	0	5202	0	0
T6	0	2	0	0
T7	0	901	0	0
T9	0	9	0	0
T10	0	121	0	0
T11	3814	0	0	0
T12	3156	0	0	0
T13	318137	0	0	0
T14	249442	0	0	0
T15	1124	0	0	0
T16	4693	0	0	0
T17	2179	0	0	0
T18	4419	0	0	0
T19	0	5	0	0
T20	0	4905	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	96205	0	0
T1	150449	166	0	0
T2	692529	1470	0	0
T3	0	25631	0	0
T5	0	4920	0	0
T7	0	897	0	0
T10	0	160	0	0
T11	3814	0	0	0
T12	3156	0	0	0
T13	318137	0	0	0
T14	249442	0	0	0
T15	1124	0	0	0
T16	4693	0	0	0
T17	2179	0	0	0
T18	4419	0	0	0
T19	0	3	0	0
T20	0	4880	0	0
T21	0	7297	0	0
T22	0	4160	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	100083	0	0
T1	150449	216	0	0
T2	692529	1261	0	0
T3	0	27854	0	0
T5	0	5169	0	0
T6	0	4	0	0
T7	0	816	0	0
T10	0	181	0	0
T11	3814	0	0	0
T12	3156	0	0	0
T13	318137	0	0	0
T14	249442	0	0	0
T15	1124	0	0	0
T16	4693	0	0	0
T17	2179	0	0	0
T18	4419	0	0	0
T20	0	4566	0	0
T21	0	7126	0	0
T23	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	94032	0	0
T1	150449	217	0	0
T2	692529	1354	0	0
T3	0	25513	0	0
T4	0	2	0	0
T5	0	4877	0	0
T6	0	6	0	0
T7	0	777	0	0
T9	0	3	0	0
T10	0	182	0	0
T11	3814	0	0	0
T12	3156	0	0	0
T13	318137	0	0	0
T14	249442	0	0	0
T15	1124	0	0	0
T16	4693	0	0	0
T17	2179	0	0	0
T18	4419	0	0	0
T20	0	4904	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149593465	96217	0	0
T1	150449	182	0	0
T2	692529	1327	0	0
T3	0	25512	0	0
T4	0	2	0	0
T5	0	5059	0	0
T7	0	802	0	0
T9	0	5	0	0
T10	0	147	0	0
T11	3814	0	0	0
T12	3156	0	0	0
T13	318137	0	0	0
T14	249442	0	0	0
T15	1124	0	0	0
T16	4693	0	0	0
T17	2179	0	0	0
T18	4419	0	0	0
T19	0	8	0	0
T20	0	4894	0	0