Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3857963	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

17077684

1

T33

1288

T34

240

T1

250

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8392500	1			T33	1503		T34	51		T1	23
values[0x0]	6170066	1			T33	267		T34	117		T1	121
values[0x1]	6373081	1			T33	240		T34	102		T1	122

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2970580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17965067

1

T33

1449

T34

244

T1

254

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	76160	1			T34	2		T13	1		T2	1
valid_sources[0x01]	166391	1			T34	1		T1	2		T2	2
valid_sources[0x02]	76569	1			T15	5		T107	1		T54	1
valid_sources[0x03]	79638	1			T1	1		T13	2		T2	4
valid_sources[0x04]	83689	1			T1	1		T13	1		T15	1
valid_sources[0x05]	75832	1			T1	1		T13	6		T2	2
valid_sources[0x06]	70344	1			T34	3		T1	1		T15	1
valid_sources[0x07]	83466	1			T15	1		T18	3		T35	1939
valid_sources[0x08]	77713	1			T34	2		T1	1		T2	1
valid_sources[0x09]	83729	1			T34	1		T13	5		T2	2
valid_sources[0x0a]	76787	1			T34	3		T2	1		T107	1
valid_sources[0x0b]	74152	1			T1	1		T2	1		T15	1
valid_sources[0x0c]	71609	1			T34	1		T2	2		T15	2
valid_sources[0x0d]	85782	1			T1	3		T13	4		T54	3
valid_sources[0x0e]	75169	1			T34	7		T1	1		T13	1
valid_sources[0x0f]	72054	1			T1	2		T13	2		T15	3
valid_sources[0x10]	73349	1			T34	1		T1	1		T13	14
valid_sources[0x11]	72761	1			T1	2		T2	2		T15	1
valid_sources[0x12]	80651	1			T1	1		T13	1		T2	1
valid_sources[0x13]	82943	1			T1	1		T2	2		T15	3
valid_sources[0x14]	72577	1			T1	1		T13	10		T35	1976
valid_sources[0x15]	76826	1			T34	3		T1	2		T13	1
valid_sources[0x16]	75155	1			T1	1		T2	1		T15	1
valid_sources[0x17]	79804	1			T34	2		T1	2		T2	2
valid_sources[0x18]	69994	1			T34	1		T1	1		T13	7
valid_sources[0x19]	77489	1			T34	2		T1	1		T13	1
valid_sources[0x1a]	79376	1			T1	1		T13	1		T15	5
valid_sources[0x1b]	77785	1			T34	1		T1	1		T2	1
valid_sources[0x1c]	72478	1			T34	1		T1	1		T2	1
valid_sources[0x1d]	77347	1			T34	3		T13	2		T2	2
valid_sources[0x1e]	76782	1			T34	3		T1	2		T2	2
valid_sources[0x1f]	79601	1			T2	2		T15	2		T18	22
valid_sources[0x20]	76162	1			T1	1		T15	1		T18	5
valid_sources[0x21]	222048	1			T1	2		T15	1		T107	1
valid_sources[0x22]	75217	1			T1	1		T13	2		T2	1
valid_sources[0x23]	74759	1			T34	1		T1	1		T2	3
valid_sources[0x24]	76750	1			T34	5		T13	1		T2	3
valid_sources[0x25]	75604	1			T34	2		T1	1		T13	3
valid_sources[0x26]	72619	1			T34	1		T15	1		T108	5
valid_sources[0x27]	82947	1			T13	2		T15	1		T107	3
valid_sources[0x28]	83639	1			T34	1		T1	1		T13	5
valid_sources[0x29]	79183	1			T1	1		T54	4		T35	1935
valid_sources[0x2a]	80540	1			T1	1		T2	1		T15	4
valid_sources[0x2b]	73203	1			T2	1		T15	2		T107	1
valid_sources[0x2c]	76456	1			T13	1		T2	3		T15	1
valid_sources[0x2d]	79701	1			T13	1		T2	1		T15	6
valid_sources[0x2e]	79751	1			T34	3		T13	2		T2	2
valid_sources[0x2f]	77389	1			T34	4		T1	1		T15	3
valid_sources[0x30]	75194	1			T1	1		T13	4		T15	5
valid_sources[0x31]	76400	1			T1	1		T13	1		T2	3
valid_sources[0x32]	83413	1			T34	1		T13	2		T18	2
valid_sources[0x33]	77700	1			T1	3		T13	9		T2	1
valid_sources[0x34]	82887	1			T15	2		T107	1		T54	2
valid_sources[0x35]	78103	1			T34	1		T2	1		T54	1
valid_sources[0x36]	76355	1			T13	2		T15	3		T18	2
valid_sources[0x37]	176750	1			T1	2		T2	1		T15	5
valid_sources[0x38]	78783	1			T34	1		T13	2		T15	1
valid_sources[0x39]	81149	1			T34	1		T13	5		T2	1
valid_sources[0x3a]	73813	1			T1	2		T13	5		T2	3
valid_sources[0x3b]	71502	1			T2	1		T15	1		T18	17
valid_sources[0x3c]	83561	1			T34	2		T1	2		T13	3
valid_sources[0x3d]	86538	1			T1	3		T13	2		T2	1
valid_sources[0x3e]	69727	1			T1	4		T2	2		T54	3
valid_sources[0x3f]	76810	1			T13	2		T15	1		T54	1
valid_sources[0x40]	79089	1			T13	5		T2	4		T15	1
valid_sources[0x41]	71549	1			T13	3		T15	3		T107	1
valid_sources[0x42]	74882	1			T34	1		T1	2		T2	1
valid_sources[0x43]	80930	1			T34	1		T2	1		T15	1
valid_sources[0x44]	78505	1			T34	1		T1	1		T13	5
valid_sources[0x45]	75826	1			T34	1		T1	1		T13	2
valid_sources[0x46]	76344	1			T34	1		T1	2		T13	2
valid_sources[0x47]	89193	1			T1	2		T13	4		T2	2
valid_sources[0x48]	80628	1			T1	4		T2	1		T15	2
valid_sources[0x49]	72600	1			T1	2		T15	4		T107	3
valid_sources[0x4a]	73497	1			T13	5		T15	5		T55	9
valid_sources[0x4b]	91549	1			T1	2		T15	4		T107	1
valid_sources[0x4c]	73994	1			T1	1		T2	1		T54	10
valid_sources[0x4d]	81322	1			T2	1		T15	2		T18	12
valid_sources[0x4e]	212813	1			T34	2		T1	2		T13	5
valid_sources[0x4f]	81140	1			T1	2		T13	5		T2	3
valid_sources[0x50]	71664	1			T34	1		T1	1		T15	1
valid_sources[0x51]	87238	1			T34	3		T13	6		T2	2
valid_sources[0x52]	75020	1			T1	1		T13	2		T18	40
valid_sources[0x53]	80543	1			T34	5		T13	1		T15	1
valid_sources[0x54]	73061	1			T34	1		T1	1		T13	3
valid_sources[0x55]	73416	1			T2	1		T15	1		T54	2
valid_sources[0x56]	77688	1			T2	1		T15	2		T107	2
valid_sources[0x57]	77029	1			T1	1		T13	3		T2	1
valid_sources[0x58]	75649	1			T34	4		T1	2		T2	2
valid_sources[0x59]	69487	1			T13	1		T2	1		T54	5
valid_sources[0x5a]	80269	1			T34	1		T13	7		T15	3
valid_sources[0x5b]	77348	1			T35	1918		T56	20		T59	3
valid_sources[0x5c]	73746	1			T1	2		T107	1		T55	2
valid_sources[0x5d]	73752	1			T15	3		T54	3		T35	2000
valid_sources[0x5e]	74441	1			T34	2		T13	2		T15	1
valid_sources[0x5f]	77965	1			T1	2		T13	2		T15	4
valid_sources[0x60]	75913	1			T34	5		T1	2		T2	2
valid_sources[0x61]	80581	1			T1	1		T13	2		T2	2
valid_sources[0x62]	251702	1			T13	1		T15	2		T107	5
valid_sources[0x63]	75713	1			T34	4		T15	1		T107	1
valid_sources[0x64]	67814	1			T1	1		T2	2		T107	1
valid_sources[0x65]	83397	1			T34	2		T1	1		T15	1
valid_sources[0x66]	73900	1			T34	1		T1	1		T35	2040
valid_sources[0x67]	75443	1			T34	2		T1	3		T2	1
valid_sources[0x68]	75539	1			T13	1		T2	1		T55	4
valid_sources[0x69]	76285	1			T2	1		T15	1		T54	4
valid_sources[0x6a]	72159	1			T34	1		T2	1		T15	4
valid_sources[0x6b]	68863	1			T34	2		T1	1		T13	4
valid_sources[0x6c]	77895	1			T34	1		T1	1		T13	1
valid_sources[0x6d]	70670	1			T34	1		T1	1		T13	2
valid_sources[0x6e]	141436	1			T11	65066		T2	1		T54	1
valid_sources[0x6f]	74247	1			T1	3		T2	1		T15	1
valid_sources[0x70]	72793	1			T34	2		T1	1		T2	2
valid_sources[0x71]	77488	1			T34	3		T1	1		T13	5
valid_sources[0x72]	84934	1			T34	2		T1	3		T13	2
valid_sources[0x73]	72007	1			T34	1		T2	1		T15	1
valid_sources[0x74]	86562	1			T34	1		T1	1		T13	3
valid_sources[0x75]	78953	1			T34	3		T1	1		T2	2
valid_sources[0x76]	78615	1			T1	1		T13	3		T54	4
valid_sources[0x77]	76375	1			T34	8		T1	1		T13	1
valid_sources[0x78]	81453	1			T34	1		T1	7		T13	4
valid_sources[0x79]	76152	1			T1	1		T2	1		T15	3
valid_sources[0x7a]	76021	1			T34	3		T1	2		T2	1
valid_sources[0x7b]	90096	1			T34	2		T2	3		T15	3
valid_sources[0x7c]	78573	1			T13	2		T2	2		T15	1
valid_sources[0x7d]	73498	1			T13	2		T15	1		T54	4
valid_sources[0x7e]	81706	1			T13	6		T15	2		T107	1
valid_sources[0x7f]	76589	1			T34	3		T1	3		T107	2
valid_sources[0x80]	71082	1			T1	1		T18	18		T54	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4785110

1

T33

781

T34

21

T1

7

values[0x0]

all_enables

biggest_size

6148700

1

T33

267

T34

117

T1

121

values[0x1]

all_enables

biggest_size

6143874

1

T33

240

T34

102

T1

122