Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	172818548	0	0	0
ctrl_en_input_filter_rd_A	172818548	66265	0	0
intr_ctrl_en_falling_rd_A	172818548	65391	0	0
intr_ctrl_en_lvlhigh_rd_A	172818548	65627	0	0
intr_ctrl_en_lvllow_rd_A	172818548	66396	0	0
intr_ctrl_en_rising_rd_A	172818548	66377	0	0
intr_enable_rd_A	172818548	66997	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	66265	0	0
T1	8293	7	0	0
T2	7219	1	0	0
T3	0	47	0	0
T4	0	89	0	0
T5	0	516	0	0
T6	0	9	0	0
T7	0	728	0	0
T8	0	7716	0	0
T9	0	3261	0	0
T10	0	3235	0	0
T11	744522	0	0	0
T12	4117	0	0	0
T13	3960	0	0	0
T14	4237	0	0	0
T15	6294	0	0	0
T16	1238	0	0	0
T17	146393	0	0	0
T18	11103	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	65391	0	0
T1	8293	9	0	0
T2	7219	0	0	0
T3	0	30	0	0
T4	0	71	0	0
T5	0	664	0	0
T7	0	864	0	0
T8	0	7433	0	0
T9	0	3218	0	0
T10	0	3465	0	0
T11	744522	0	0	0
T12	4117	0	0	0
T13	3960	0	0	0
T14	4237	0	0	0
T15	6294	0	0	0
T16	1238	0	0	0
T17	146393	0	0	0
T18	11103	0	0	0
T19	0	2	0	0
T20	0	1825	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	65627	0	0
T3	9944	30	0	0
T4	0	59	0	0
T5	0	561	0	0
T7	0	731	0	0
T8	0	7724	0	0
T9	0	3253	0	0
T10	0	3201	0	0
T20	0	1912	0	0
T21	0	7	0	0
T22	0	72	0	0
T23	726	0	0	0
T24	2023	0	0	0
T25	3628	0	0	0
T26	7000	0	0	0
T27	35561	0	0	0
T28	5304	0	0	0
T29	210394	0	0	0
T30	4409	0	0	0
T31	8248	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	66396	0	0
T3	9944	25	0	0
T4	0	67	0	0
T5	0	463	0	0
T7	0	873	0	0
T8	0	7465	0	0
T9	0	3367	0	0
T10	0	3482	0	0
T19	0	6	0	0
T20	0	1793	0	0
T21	0	1	0	0
T23	726	0	0	0
T24	2023	0	0	0
T25	3628	0	0	0
T26	7000	0	0	0
T27	35561	0	0	0
T28	5304	0	0	0
T29	210394	0	0	0
T30	4409	0	0	0
T31	8248	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	66377	0	0
T3	9944	55	0	0
T4	0	100	0	0
T5	0	571	0	0
T7	0	753	0	0
T8	0	7332	0	0
T9	0	3484	0	0
T10	0	3373	0	0
T20	0	2312	0	0
T22	0	42	0	0
T23	726	0	0	0
T24	2023	0	0	0
T25	3628	0	0	0
T26	7000	0	0	0
T27	35561	0	0	0
T28	5304	0	0	0
T29	210394	0	0	0
T30	4409	0	0	0
T31	8248	0	0	0
T32	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172818548	66997	0	0
T1	8293	2	0	0
T2	7219	9	0	0
T3	0	60	0	0
T4	0	129	0	0
T5	0	651	0	0
T7	0	687	0	0
T8	0	7202	0	0
T9	0	3552	0	0
T10	0	3210	0	0
T11	744522	0	0	0
T12	4117	0	0	0
T13	3960	0	0	0
T14	4237	0	0	0
T15	6294	0	0	0
T16	1238	0	0	0
T17	146393	0	0	0
T18	11103	0	0	0
T20	0	2028	0	0