Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	142075286	0	0	0
ctrl_en_input_filter_rd_A	142075286	50143	0	0
intr_ctrl_en_falling_rd_A	142075286	51817	0	0
intr_ctrl_en_lvlhigh_rd_A	142075286	51408	0	0
intr_ctrl_en_lvllow_rd_A	142075286	52245	0	0
intr_ctrl_en_rising_rd_A	142075286	51063	0	0
intr_enable_rd_A	142075286	50534	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	50143	0	0
T1	168727	4938	0	0
T2	35542	232	0	0
T3	140202	3670	0	0
T4	0	4	0	0
T5	0	1	0	0
T6	0	1478	0	0
T7	0	468	0	0
T8	0	232	0	0
T9	0	17709	0	0
T10	0	2306	0	0
T11	2459	0	0	0
T12	184772	0	0	0
T13	2838	0	0	0
T14	8032	0	0	0
T15	1936	0	0	0
T16	8915	0	0	0
T17	3275	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	51817	0	0
T1	168727	4770	0	0
T2	35542	278	0	0
T3	140202	3901	0	0
T4	0	15	0	0
T5	0	2	0	0
T6	0	1479	0	0
T7	0	369	0	0
T8	0	192	0	0
T9	0	19149	0	0
T10	0	2418	0	0
T11	2459	0	0	0
T12	184772	0	0	0
T13	2838	0	0	0
T14	8032	0	0	0
T15	1936	0	0	0
T16	8915	0	0	0
T17	3275	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	51408	0	0
T1	168727	4822	0	0
T2	35542	197	0	0
T3	140202	3981	0	0
T4	0	4	0	0
T6	0	1471	0	0
T7	0	413	0	0
T8	0	176	0	0
T9	0	18534	0	0
T10	0	2493	0	0
T11	2459	0	0	0
T12	184772	0	0	0
T13	2838	0	0	0
T14	8032	0	0	0
T15	1936	0	0	0
T16	8915	0	0	0
T17	3275	0	0	0
T18	0	5	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	52245	0	0
T1	168727	4945	0	0
T2	35542	239	0	0
T3	140202	4063	0	0
T4	0	4	0	0
T5	0	5	0	0
T6	0	1459	0	0
T7	0	454	0	0
T8	0	170	0	0
T9	0	19159	0	0
T10	0	2375	0	0
T11	2459	0	0	0
T12	184772	0	0	0
T13	2838	0	0	0
T14	8032	0	0	0
T15	1936	0	0	0
T16	8915	0	0	0
T17	3275	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	51063	0	0
T1	168727	4797	0	0
T2	35542	278	0	0
T3	140202	4147	0	0
T4	0	10	0	0
T6	0	1593	0	0
T7	0	390	0	0
T8	0	242	0	0
T9	0	17909	0	0
T10	0	2367	0	0
T11	2459	0	0	0
T12	184772	0	0	0
T13	2838	0	0	0
T14	8032	0	0	0
T15	1936	0	0	0
T16	8915	0	0	0
T17	3275	0	0	0
T18	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	142075286	50534	0	0
T1	168727	4854	0	0
T2	35542	266	0	0
T3	140202	4390	0	0
T5	0	8	0	0
T6	0	1346	0	0
T7	0	433	0	0
T8	0	175	0	0
T9	0	17509	0	0
T10	0	2297	0	0
T11	2459	0	0	0
T12	184772	0	0	0
T13	2838	0	0	0
T14	8032	0	0	0
T15	1936	0	0	0
T16	8915	0	0	0
T17	3275	0	0	0
T18	0	1	0	0