Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3445310	1			T26	1		T27	59		T28	44
all_pins[1]	3445310	1			T26	1		T27	59		T28	44
all_pins[2]	3445310	1			T26	1		T27	59		T28	44
all_pins[3]	3445310	1			T26	1		T27	59		T28	44
all_pins[4]	3445310	1			T26	1		T27	59		T28	44
all_pins[5]	3445310	1			T26	1		T27	59		T28	44
all_pins[6]	3445310	1			T26	1		T27	59		T28	44
all_pins[7]	3445310	1			T26	1		T27	59		T28	44
all_pins[8]	3445310	1			T26	1		T27	59		T28	44
all_pins[9]	3445310	1			T26	1		T27	59		T28	44
all_pins[10]	3445310	1			T26	1		T27	59		T28	44
all_pins[11]	3445310	1			T26	1		T27	59		T28	44
all_pins[12]	3445310	1			T26	1		T27	59		T28	44
all_pins[13]	3445310	1			T26	1		T27	59		T28	44
all_pins[14]	3445310	1			T26	1		T27	59		T28	44
all_pins[15]	3445310	1			T26	1		T27	59		T28	44
all_pins[16]	3445310	1			T26	1		T27	59		T28	44
all_pins[17]	3445310	1			T26	1		T27	59		T28	44
all_pins[18]	3445310	1			T26	1		T27	59		T28	44
all_pins[19]	3445310	1			T26	1		T27	59		T28	44
all_pins[20]	3445310	1			T26	1		T27	59		T28	44
all_pins[21]	3445310	1			T26	1		T27	59		T28	44
all_pins[22]	3445310	1			T26	1		T27	59		T28	44
all_pins[23]	3445310	1			T26	1		T27	59		T28	44
all_pins[24]	3445310	1			T26	1		T27	59		T28	44
all_pins[25]	3445310	1			T26	1		T27	59		T28	44
all_pins[26]	3445310	1			T26	1		T27	59		T28	44
all_pins[27]	3445310	1			T26	1		T27	59		T28	44
all_pins[28]	3445310	1			T26	1		T27	59		T28	44
all_pins[29]	3445310	1			T26	1		T27	59		T28	44
all_pins[30]	3445310	1			T26	1		T27	59		T28	44
all_pins[31]	3445310	1			T26	1		T27	59		T28	44

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	68464945	1			T26	32		T27	1037		T28	746
values[0x1]	41784975	1			T27	851		T28	662		T29	309
transitions[0x0=>0x1]	25037449	1			T27	443		T28	304		T29	257
transitions[0x1=>0x0]	25037291	1			T27	442		T28	304		T29	257

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2139771	1			T26	1		T27	34		T28	24
all_pins[0]	values[0x1]	1305539	1			T27	25		T28	20		T29	5
all_pins[0]	transitions[0x0=>0x1]	805927	1			T27	16		T28	13		T29	5
all_pins[0]	transitions[0x1=>0x0]	811157	1			T27	14		T28	7		T29	10
all_pins[1]	values[0x0]	2135010	1			T26	1		T27	33		T28	16
all_pins[1]	values[0x1]	1310300	1			T27	26		T28	28		T29	13
all_pins[1]	transitions[0x0=>0x1]	781420	1			T27	13		T28	14		T29	12
all_pins[1]	transitions[0x1=>0x0]	776659	1			T27	12		T28	6		T29	4
all_pins[2]	values[0x0]	2139114	1			T26	1		T27	33		T28	25
all_pins[2]	values[0x1]	1306196	1			T27	26		T28	19		T29	3
all_pins[2]	transitions[0x0=>0x1]	781155	1			T27	14		T28	8		T29	3
all_pins[2]	transitions[0x1=>0x0]	785259	1			T27	14		T28	17		T29	13
all_pins[3]	values[0x0]	2142717	1			T26	1		T27	30		T28	22
all_pins[3]	values[0x1]	1302593	1			T27	29		T28	22		T29	7
all_pins[3]	transitions[0x0=>0x1]	779824	1			T27	16		T28	12		T29	7
all_pins[3]	transitions[0x1=>0x0]	783427	1			T27	13		T28	9		T29	3
all_pins[4]	values[0x0]	2139024	1			T26	1		T27	29		T28	26
all_pins[4]	values[0x1]	1306286	1			T27	30		T28	18		T29	12
all_pins[4]	transitions[0x0=>0x1]	781780	1			T27	13		T28	9		T29	12
all_pins[4]	transitions[0x1=>0x0]	778087	1			T27	12		T28	13		T29	7
all_pins[5]	values[0x0]	2137901	1			T26	1		T27	37		T28	28
all_pins[5]	values[0x1]	1307409	1			T27	22		T28	16		T29	4
all_pins[5]	transitions[0x0=>0x1]	782115	1			T27	9		T28	10		T29	4
all_pins[5]	transitions[0x1=>0x0]	780992	1			T27	17		T28	12		T29	12
all_pins[6]	values[0x0]	2138346	1			T26	1		T27	34		T28	27
all_pins[6]	values[0x1]	1306964	1			T27	25		T28	17		T29	8
all_pins[6]	transitions[0x0=>0x1]	780714	1			T27	12		T28	8		T29	8
all_pins[6]	transitions[0x1=>0x0]	781159	1			T27	9		T28	7		T29	4
all_pins[7]	values[0x0]	2145232	1			T26	1		T27	33		T28	30
all_pins[7]	values[0x1]	1300078	1			T27	26		T28	14		T29	18
all_pins[7]	transitions[0x0=>0x1]	778731	1			T27	15		T28	7		T29	17
all_pins[7]	transitions[0x1=>0x0]	785617	1			T27	14		T28	10		T29	7
all_pins[8]	values[0x0]	2139443	1			T26	1		T27	30		T28	22
all_pins[8]	values[0x1]	1305867	1			T27	29		T28	22		T29	9
all_pins[8]	transitions[0x0=>0x1]	782729	1			T27	17		T28	13		T29	4
all_pins[8]	transitions[0x1=>0x0]	776940	1			T27	14		T28	5		T29	13
all_pins[9]	values[0x0]	2140721	1			T26	1		T27	35		T28	22
all_pins[9]	values[0x1]	1304589	1			T27	24		T28	22		T29	11
all_pins[9]	transitions[0x0=>0x1]	781876	1			T27	8		T28	9		T29	8
all_pins[9]	transitions[0x1=>0x0]	783154	1			T27	13		T28	9		T29	6
all_pins[10]	values[0x0]	2142757	1			T26	1		T27	38		T28	15
all_pins[10]	values[0x1]	1302553	1			T27	21		T28	29		T29	4
all_pins[10]	transitions[0x0=>0x1]	779947	1			T27	13		T28	13		T29	4
all_pins[10]	transitions[0x1=>0x0]	781983	1			T27	16		T28	6		T29	11
all_pins[11]	values[0x0]	2141705	1			T26	1		T27	40		T28	18
all_pins[11]	values[0x1]	1303605	1			T27	19		T28	26		T29	10
all_pins[11]	transitions[0x0=>0x1]	781045	1			T27	10		T28	4		T29	10
all_pins[11]	transitions[0x1=>0x0]	779993	1			T27	12		T28	7		T29	4
all_pins[12]	values[0x0]	2139996	1			T26	1		T27	40		T28	24
all_pins[12]	values[0x1]	1305314	1			T27	19		T28	20		T29	9
all_pins[12]	transitions[0x0=>0x1]	783258	1			T27	11		T28	8		T29	2
all_pins[12]	transitions[0x1=>0x0]	781549	1			T27	11		T28	14		T29	3
all_pins[13]	values[0x0]	2136350	1			T26	1		T27	29		T28	25
all_pins[13]	values[0x1]	1308960	1			T27	30		T28	19		T29	9
all_pins[13]	transitions[0x0=>0x1]	783790	1			T27	19		T28	7		T29	9
all_pins[13]	transitions[0x1=>0x0]	780144	1			T27	8		T28	8		T29	9
all_pins[14]	values[0x0]	2137403	1			T26	1		T27	23		T28	29
all_pins[14]	values[0x1]	1307907	1			T27	36		T28	15		T29	8
all_pins[14]	transitions[0x0=>0x1]	781303	1			T27	22		T28	3		T29	5
all_pins[14]	transitions[0x1=>0x0]	782356	1			T27	16		T28	7		T29	6
all_pins[15]	values[0x0]	2140873	1			T26	1		T27	34		T28	30
all_pins[15]	values[0x1]	1304437	1			T27	25		T28	14		T29	18
all_pins[15]	transitions[0x0=>0x1]	780370	1			T27	11		T28	8		T29	15
all_pins[15]	transitions[0x1=>0x0]	783840	1			T27	22		T28	9		T29	5
all_pins[16]	values[0x0]	2137165	1			T26	1		T27	27		T28	23
all_pins[16]	values[0x1]	1308145	1			T27	32		T28	21		T29	9
all_pins[16]	transitions[0x0=>0x1]	783727	1			T27	21		T28	11		T29	8
all_pins[16]	transitions[0x1=>0x0]	780019	1			T27	14		T28	4		T29	17
all_pins[17]	values[0x0]	2140044	1			T26	1		T27	33		T28	20
all_pins[17]	values[0x1]	1305266	1			T27	26		T28	24		T29	11
all_pins[17]	transitions[0x0=>0x1]	779815	1			T27	12		T28	15		T29	9
all_pins[17]	transitions[0x1=>0x0]	782694	1			T27	18		T28	12		T29	7
all_pins[18]	values[0x0]	2140974	1			T26	1		T27	27		T28	21
all_pins[18]	values[0x1]	1304336	1			T27	32		T28	23		T29	17
all_pins[18]	transitions[0x0=>0x1]	780971	1			T27	17		T28	13		T29	15
all_pins[18]	transitions[0x1=>0x0]	781901	1			T27	11		T28	14		T29	9
all_pins[19]	values[0x0]	2145210	1			T26	1		T27	29		T28	26
all_pins[19]	values[0x1]	1300100	1			T27	30		T28	18		T29	3
all_pins[19]	transitions[0x0=>0x1]	779303	1			T27	15		T28	5		T29	3
all_pins[19]	transitions[0x1=>0x0]	783539	1			T27	17		T28	10		T29	17
all_pins[20]	values[0x0]	2148542	1			T26	1		T27	36		T28	17
all_pins[20]	values[0x1]	1296768	1			T27	23		T28	27		T29	14
all_pins[20]	transitions[0x0=>0x1]	778222	1			T27	11		T28	17		T29	13
all_pins[20]	transitions[0x1=>0x0]	781554	1			T27	18		T28	8		T29	2
all_pins[21]	values[0x0]	2138684	1			T26	1		T27	27		T28	20
all_pins[21]	values[0x1]	1306626	1			T27	32		T28	24		T29	8
all_pins[21]	transitions[0x0=>0x1]	785598	1			T27	20		T28	3		T29	6
all_pins[21]	transitions[0x1=>0x0]	775740	1			T27	11		T28	6		T29	12
all_pins[22]	values[0x0]	2140787	1			T26	1		T27	26		T28	21
all_pins[22]	values[0x1]	1304523	1			T27	33		T28	23		T29	11
all_pins[22]	transitions[0x0=>0x1]	780967	1			T27	13		T28	9		T29	11
all_pins[22]	transitions[0x1=>0x0]	783070	1			T27	12		T28	10		T29	8
all_pins[23]	values[0x0]	2139926	1			T26	1		T27	32		T28	18
all_pins[23]	values[0x1]	1305384	1			T27	27		T28	26		T29	11
all_pins[23]	transitions[0x0=>0x1]	782766	1			T27	14		T28	12		T29	11
all_pins[23]	transitions[0x1=>0x0]	781905	1			T27	20		T28	9		T29	11
all_pins[24]	values[0x0]	2138986	1			T26	1		T27	36		T28	27
all_pins[24]	values[0x1]	1306324	1			T27	23		T28	17		T29	10
all_pins[24]	transitions[0x0=>0x1]	783877	1			T27	11		T28	7		T29	7
all_pins[24]	transitions[0x1=>0x0]	782937	1			T27	15		T28	16		T29	8
all_pins[25]	values[0x0]	2139121	1			T26	1		T27	39		T28	27
all_pins[25]	values[0x1]	1306189	1			T27	20		T28	17		T29	6
all_pins[25]	transitions[0x0=>0x1]	781408	1			T27	11		T28	9		T29	5
all_pins[25]	transitions[0x1=>0x0]	781543	1			T27	14		T28	9		T29	9
all_pins[26]	values[0x0]	2134305	1			T26	1		T27	33		T28	28
all_pins[26]	values[0x1]	1311005	1			T27	26		T28	16		T29	21
all_pins[26]	transitions[0x0=>0x1]	783560	1			T27	15		T28	8		T29	17
all_pins[26]	transitions[0x1=>0x0]	778744	1			T27	9		T28	9		T29	2
all_pins[27]	values[0x0]	2138301	1			T26	1		T27	30		T28	26
all_pins[27]	values[0x1]	1307009	1			T27	29		T28	18		T29	5
all_pins[27]	transitions[0x0=>0x1]	778360	1			T27	13		T28	15		T29	1
all_pins[27]	transitions[0x1=>0x0]	782356	1			T27	10		T28	13		T29	17
all_pins[28]	values[0x0]	2135575	1			T26	1		T27	28		T28	18
all_pins[28]	values[0x1]	1309735	1			T27	31		T28	26		T29	11
all_pins[28]	transitions[0x0=>0x1]	782139	1			T27	12		T28	12		T29	11
all_pins[28]	transitions[0x1=>0x0]	779413	1			T27	10		T28	4		T29	5
all_pins[29]	values[0x0]	2139048	1			T26	1		T27	34		T28	22
all_pins[29]	values[0x1]	1306262	1			T27	25		T28	22		T29	2
all_pins[29]	transitions[0x0=>0x1]	782039	1			T27	9		T28	7		T30	12
all_pins[29]	transitions[0x1=>0x0]	785512	1			T27	15		T28	11		T29	9
all_pins[30]	values[0x0]	2137531	1			T26	1		T27	33		T28	19
all_pins[30]	values[0x1]	1307779	1			T27	26		T28	25		T29	12
all_pins[30]	transitions[0x0=>0x1]	783858	1			T27	15		T28	10		T29	11
all_pins[30]	transitions[0x1=>0x0]	782341	1			T27	14		T28	7		T29	1
all_pins[31]	values[0x0]	2134383	1			T26	1		T27	35		T28	30
all_pins[31]	values[0x1]	1310927	1			T27	24		T28	14		T29	10
all_pins[31]	transitions[0x0=>0x1]	784855	1			T27	15		T28	5		T29	4
all_pins[31]	transitions[0x1=>0x0]	781707	1			T27	17		T28	16		T29	6