| | | | | | | | |
tb |
99.56 |
99.06 |
99.24 |
100.00 |
|
99.80 |
99.68 |
| dut |
99.56 |
99.06 |
99.24 |
100.00 |
|
99.80 |
99.68 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_filter[0].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[10].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[11].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[12].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[13].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[14].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[15].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[16].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[17].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[18].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[19].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[1].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[20].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[21].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[22].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[23].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[24].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[25].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[26].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[27].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[28].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[29].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[2].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[30].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[31].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[3].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[4].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[5].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[6].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[7].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[8].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gen_filter[9].u_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| gpio_csr_assert |
85.71 |
|
|
|
|
|
85.71 |
| intr_hw |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_reg |
99.03 |
97.69 |
98.53 |
100.00 |
|
98.95 |
100.00 |
| u_alert_test |
100.00 |
100.00 |
|
|
|
|
|
| u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
| u_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_ctrl_en_input_filter |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_data_in |
67.59 |
77.78 |
50.00 |
|
|
75.00 |
|
| wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
| u_direct_oe |
100.00 |
100.00 |
|
|
|
|
|
| u_direct_out |
100.00 |
100.00 |
|
|
|
|
|
| u_intr_ctrl_en_falling |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_ctrl_en_lvlhigh |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_ctrl_en_lvllow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_ctrl_en_rising |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_enable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_state |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_test |
100.00 |
100.00 |
|
|
|
|
|
| u_masked_oe_lower_data |
100.00 |
100.00 |
|
|
|
|
|
| u_masked_oe_lower_mask |
75.00 |
75.00 |
|
|
|
|
|
| u_masked_oe_upper_data |
100.00 |
100.00 |
|
|
|
|
|
| u_masked_oe_upper_mask |
75.00 |
75.00 |
|
|
|
|
|
| u_masked_out_lower_data |
100.00 |
100.00 |
|
|
|
|
|
| u_masked_out_lower_mask |
66.67 |
66.67 |
|
|
|
|
|
| u_masked_out_upper_data |
100.00 |
100.00 |
|
|
|
|
|
| u_masked_out_upper_mask |
66.67 |
66.67 |
|
|
|
|
|
| u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
| u_reg_if |
98.67 |
97.14 |
97.53 |
|
|
100.00 |
100.00 |
| u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
| u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
| u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|