Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[1]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[2]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[3]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[4]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[5]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[6]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[7]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[8]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[9]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[10]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[11]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[12]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[13]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[14]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[15]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[16]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[17]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[18]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[19]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[20]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[21]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[22]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[23]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[24]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[25]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[26]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[27]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[28]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[29]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[30]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[31]	11776405	1			T26	591		T27	825		T28	592

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221339314

1

T26

13426

T27

13018

T28

9333

auto[1]

155505646

1

T26

5486

T27

13382

T28

9611

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304397014

1

T26

11214

T27

26400

T28

18944

auto[1]

72447946

1

T26

7698

T29

200

T1

103034

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

283132121

1

T26

11202

T27

26400

T28

18944

auto[1]

93712839

1

T26

7710

T29

769

T1

131541

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4378968	1			T26	188		T27	418		T28	258
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3331191	1			T26	48		T27	407		T28	334
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1136296	1			T26	120		T29	1		T1	16398
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1404765	1			T26	107		T29	2		T1	23285
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	394727	1			T29	20		T1	1552		T11	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1130458	1			T26	128		T29	7		T1	15908
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4379916	1			T26	193		T27	399		T28	331
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3325591	1			T26	49		T27	426		T28	261
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1141553	1			T26	137		T29	1		T1	16182
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1405593	1			T26	100		T29	1		T1	22884
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	395314	1			T29	18		T1	1494		T11	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1128438	1			T26	112		T29	10		T1	15826
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4371856	1			T26	162		T27	399		T28	318
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3331907	1			T26	52		T27	426		T28	274
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1137522	1			T26	114		T29	4		T1	15643
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1409868	1			T26	128		T29	1		T1	23808
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	395414	1			T29	17		T1	1619		T11	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1129838	1			T26	135		T29	3		T1	16515
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4374736	1			T26	170		T27	438		T28	302
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3334267	1			T26	55		T27	387		T28	290
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1136430	1			T26	110		T29	6		T1	16244
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1405129	1			T26	142		T29	15		T1	23263
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	397359	1			T29	6		T1	1469		T11	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1128484	1			T26	114		T1	16380		T11	36
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4367827	1			T26	189		T27	423		T28	326
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3337994	1			T26	52		T27	402		T28	266
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1141396	1			T26	130		T29	1		T1	16321
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1401306	1			T26	110		T29	12		T1	23068
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	398351	1			T29	9		T1	1493		T11	18
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1129531	1			T26	110		T29	3		T1	15810
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4371070	1			T26	181		T27	414		T28	219
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3334448	1			T26	62		T27	411		T28	373
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1132861	1			T26	108		T29	15		T1	16238
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1408219	1			T26	136		T29	31		T1	23338
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	397443	1			T29	12		T1	1464		T11	13
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1132364	1			T26	104		T1	16568		T11	34
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4376621	1			T26	151		T27	382		T28	342
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3339852	1			T26	57		T27	443		T28	250
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1142040	1			T26	148		T29	2		T1	16732
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1396633	1			T26	110		T29	9		T1	23666
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	397685	1			T29	10		T1	1607		T11	16
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1123574	1			T26	125		T29	9		T1	16238
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4376943	1			T26	162		T27	388		T28	288
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3331280	1			T26	50		T27	437		T28	304
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1139124	1			T26	139		T1	16337		T11	49
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1405693	1			T26	106		T29	15		T1	23074
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	396161	1			T29	1		T1	1497		T11	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1127204	1			T26	134		T1	15856		T11	30
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4372180	1			T26	192		T27	364		T28	242
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3335801	1			T26	45		T27	461		T28	350
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1140708	1			T26	138		T29	1		T1	16376
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1403871	1			T26	110		T29	7		T1	23092
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	396685	1			T29	5		T1	1524		T11	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1127160	1			T26	106		T29	3		T1	16054
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4368364	1			T26	210		T27	429		T28	311
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3337598	1			T26	55		T27	396		T28	281
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1141508	1			T26	94		T29	9		T1	16096
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1400227	1			T26	134		T29	21		T1	23294
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	397235	1			T29	14		T1	1522		T11	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1131473	1			T26	98		T29	8		T1	15322
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4377185	1			T26	189		T27	382		T28	308
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3336658	1			T26	49		T27	443		T28	284
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1137169	1			T26	85		T1	15701		T11	40
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1401319	1			T26	148		T29	32		T1	23945
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	398283	1			T29	6		T1	1482		T11	9
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1125791	1			T26	120		T1	16386		T11	63
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4374182	1			T26	147		T27	373		T28	301
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3332334	1			T26	47		T27	452		T28	291
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1138317	1			T26	113		T29	5		T1	15939
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1402758	1			T26	140		T29	6		T1	23423
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	396211	1			T29	7		T1	1493		T11	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1132603	1			T26	144		T29	9		T1	16362
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4373852	1			T26	194		T27	380		T28	302
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3330264	1			T26	44		T27	445		T28	290
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1142052	1			T26	122		T29	18		T1	16480
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1403842	1			T26	108		T29	12		T1	23349
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	396748	1			T29	4		T1	1537		T11	21
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1129647	1			T26	123		T29	3		T1	15785
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4374549	1			T26	152		T27	397		T28	359
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3333766	1			T26	52		T27	428		T28	233
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1137076	1			T26	108		T29	11		T1	16334
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1403476	1			T26	131		T29	2		T1	23474
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	397417	1			T29	3		T1	1517		T11	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1130121	1			T26	148		T29	4		T1	16023
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4368125	1			T26	179		T27	400		T28	292
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3337244	1			T26	47		T27	425		T28	300
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1138778	1			T26	118		T29	5		T1	15853
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1406813	1			T26	129		T29	12		T1	23830
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	396644	1			T29	18		T1	1521		T11	22
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1128801	1			T26	118		T29	9		T1	16214
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4385830	1			T26	175		T27	456		T28	325
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3326868	1			T26	59		T27	369		T28	267
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1142833	1			T26	142		T29	5		T1	15794
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1401614	1			T26	80		T29	22		T1	23824
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	395495	1			T29	1		T1	1563		T11	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1123765	1			T26	135		T1	15989		T11	30
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4380666	1			T26	184		T27	395		T28	285
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3331783	1			T26	58		T27	430		T28	307
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1135708	1			T26	114		T29	1		T1	16203
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1406088	1			T26	128		T29	14		T1	23425
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	395994	1			T29	8		T1	1562		T11	18
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1126166	1			T26	107		T1	15866		T11	38
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4378146	1			T26	140		T27	450		T28	287
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3336780	1			T26	68		T27	375		T28	305
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1136032	1			T26	159		T1	16164		T11	36
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1401977	1			T26	114		T29	4		T1	23684
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	397210	1			T29	17		T1	1459		T11	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1126260	1			T26	110		T1	15854		T11	36
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4384486	1			T26	178		T27	403		T28	264
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3326169	1			T26	49		T27	422		T28	328
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1139048	1			T26	108		T29	5		T1	16248
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1404195	1			T26	144		T29	2		T1	23260
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	395258	1			T29	1		T1	1641		T11	18
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1127249	1			T26	112		T1	16488		T11	44
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4383925	1			T26	174		T27	372		T28	261
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3333188	1			T26	52		T27	453		T28	331
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1133863	1			T26	129		T29	2		T1	16102
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1406552	1			T26	112		T29	14		T1	23990
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	396279	1			T29	5		T1	1611		T11	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1122598	1			T26	124		T1	15896		T11	42
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4368166	1			T26	148		T27	449		T28	309
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3339165	1			T26	54		T27	376		T28	283
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1131253	1			T26	122		T1	16388		T11	27
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1407764	1			T26	129		T29	8		T1	23080
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	399165	1			T29	21		T1	1619		T11	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1130892	1			T26	138		T1	16413		T11	28
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4377321	1			T26	167		T27	376		T28	250
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3338513	1			T26	59		T27	449		T28	342
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1134457	1			T26	113		T1	16099		T11	18
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1408744	1			T26	140		T29	17		T1	23141
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	397228	1			T29	8		T1	1551		T11	25
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1120142	1			T26	112		T1	16249		T11	47
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4382678	1			T26	207		T27	469		T28	273
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3340611	1			T26	48		T27	356		T28	319
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1135727	1			T26	140		T1	15786		T11	62
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1403026	1			T26	112		T29	2		T1	23677
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	397290	1			T29	21		T1	1642		T11	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1117073	1			T26	84		T29	5		T1	15718
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4368037	1			T26	184		T27	374		T28	337
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3342626	1			T26	52		T27	451		T28	255
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1131566	1			T26	120		T29	9		T1	15744
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1409808	1			T26	119		T29	10		T1	23928
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	397784	1			T29	7		T1	1470		T11	23
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1126584	1			T26	116		T1	16111		T11	66
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4373018	1			T26	210		T27	454		T28	268
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3340649	1			T26	38		T27	371		T28	324
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1135542	1			T26	128		T29	3		T1	15817
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1402631	1			T26	106		T29	4		T1	23908
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	397057	1			T29	2		T1	1589		T11	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1127508	1			T26	109		T1	16223		T11	66
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4370877	1			T26	154		T27	348		T28	326
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3339037	1			T26	56		T27	477		T28	266
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1132471	1			T26	117		T1	16335		T11	55
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1410133	1			T26	136		T29	28		T1	23014
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	398997	1			T29	21		T1	1335		T11	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1124890	1			T26	128		T29	4		T1	15271
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4363701	1			T26	163		T27	467		T28	253
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3348810	1			T26	53		T27	358		T28	339
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1138702	1			T26	140		T1	16119		T11	20
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1404125	1			T26	99		T29	1		T1	23399
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	396319	1			T29	5		T1	1599		T11	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1124748	1			T26	136		T29	5		T1	15997
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4366315	1			T26	203		T27	392		T28	257
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3345325	1			T26	48		T27	433		T28	335
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1137140	1			T26	88		T1	16600		T11	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1403937	1			T26	136		T29	11		T1	23184
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	398092	1			T29	5		T1	1607		T11	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1125596	1			T26	116		T29	3		T1	16311
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4381349	1			T26	163		T27	415		T28	266
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3336724	1			T26	58		T27	410		T28	326
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1138238	1			T26	130		T29	3		T1	16067
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1399597	1			T26	130		T29	10		T1	24002
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	392691	1			T29	14		T1	1597		T11	16
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1127806	1			T26	110		T29	2		T1	16015
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4374341	1			T26	149		T27	390		T28	280
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3336751	1			T26	52		T27	435		T28	312
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1133300	1			T26	102		T29	3		T1	16154
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1410983	1			T26	138		T29	8		T1	24126
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	396360	1			T29	4		T1	1683		T11	7
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1124670	1			T26	150		T1	16089		T11	42
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4375225	1			T26	191		T27	426		T28	293
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3335214	1			T26	53		T27	399		T28	299
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1135009	1			T26	116		T29	1		T1	15968
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1412647	1			T26	123		T29	13		T1	23600
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	397282	1			T29	15		T1	1527		T11	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1121028	1			T26	108		T1	16040		T11	43
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4371323	1			T26	193		T27	396		T28	300
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3341297	1			T26	53		T27	429		T28	292
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1136919	1			T26	134		T29	2		T1	15793
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1403565	1			T26	113		T29	11		T1	23968
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	398455	1			T29	20		T1	1479		T11	15
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1124846	1			T26	98		T1	16313		T11	15

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal