Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[1]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[2]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[3]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[4]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[5]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[6]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[7]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[8]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[9]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[10]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[11]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[12]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[13]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[14]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[15]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[16]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[17]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[18]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[19]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[20]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[21]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[22]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[23]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[24]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[25]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[26]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[27]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[28]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[29]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[30]	11776405	1			T26	591		T27	825		T28	592
bins_for_gpio_bits[31]	11776405	1			T26	591		T27	825		T28	592

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221339314

1

T26

13426

T27

13018

T28

9333

auto[1]

155505646

1

T26

5486

T27

13382

T28

9611

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221332084

1

T26

13420

T27

13018

T28

9333

auto[1]

155512876

1

T26

5492

T27

13382

T28

9611

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6717793	1			T26	385		T27	418		T28	258
bins_for_gpio_bits[0]	auto[0]	auto[1]	202006	1			T26	30		T1	2864		T11	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	202236	1			T26	30		T1	2877		T11	8
bins_for_gpio_bits[0]	auto[1]	auto[1]	4654370	1			T26	146		T27	407		T28	334
bins_for_gpio_bits[1]	auto[0]	auto[0]	6724832	1			T26	402		T27	399		T28	331
bins_for_gpio_bits[1]	auto[0]	auto[1]	201984	1			T26	28		T1	2788		T11	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	202230	1			T26	28		T1	2800		T11	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	4647359	1			T26	133		T27	426		T28	261
bins_for_gpio_bits[2]	auto[0]	auto[0]	6717128	1			T26	372		T27	399		T28	318
bins_for_gpio_bits[2]	auto[0]	auto[1]	201907	1			T26	31		T1	2860		T11	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	202118	1			T26	32		T1	2875		T11	8
bins_for_gpio_bits[2]	auto[1]	auto[1]	4655252	1			T26	156		T27	426		T28	274
bins_for_gpio_bits[3]	auto[0]	auto[0]	6713470	1			T26	397		T27	438		T28	302
bins_for_gpio_bits[3]	auto[0]	auto[1]	202632	1			T26	25		T1	2829		T11	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	202825	1			T26	25		T1	2845		T11	6
bins_for_gpio_bits[3]	auto[1]	auto[1]	4657478	1			T26	144		T27	387		T28	290
bins_for_gpio_bits[4]	auto[0]	auto[0]	6708315	1			T26	402		T27	423		T28	326
bins_for_gpio_bits[4]	auto[0]	auto[1]	201970	1			T26	27		T1	2834		T11	5
bins_for_gpio_bits[4]	auto[1]	auto[0]	202214	1			T26	27		T1	2846		T11	5
bins_for_gpio_bits[4]	auto[1]	auto[1]	4663906	1			T26	135		T27	402		T28	266
bins_for_gpio_bits[5]	auto[0]	auto[0]	6709071	1			T26	392		T27	414		T28	219
bins_for_gpio_bits[5]	auto[0]	auto[1]	202817	1			T26	33		T1	2872		T11	7
bins_for_gpio_bits[5]	auto[1]	auto[0]	203079	1			T26	33		T1	2885		T11	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	4661438	1			T26	133		T27	411		T28	373
bins_for_gpio_bits[6]	auto[0]	auto[0]	6713449	1			T26	373		T27	382		T28	342
bins_for_gpio_bits[6]	auto[0]	auto[1]	201596	1			T26	35		T1	2890		T11	8
bins_for_gpio_bits[6]	auto[1]	auto[0]	201845	1			T26	36		T1	2905		T11	8
bins_for_gpio_bits[6]	auto[1]	auto[1]	4659515	1			T26	147		T27	443		T28	250
bins_for_gpio_bits[7]	auto[0]	auto[0]	6719431	1			T26	374		T27	388		T28	288
bins_for_gpio_bits[7]	auto[0]	auto[1]	202101	1			T26	33		T1	2855		T11	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	202329	1			T26	33		T1	2871		T11	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	4652544	1			T26	151		T27	437		T28	304
bins_for_gpio_bits[8]	auto[0]	auto[0]	6714637	1			T26	409		T27	364		T28	242
bins_for_gpio_bits[8]	auto[0]	auto[1]	201894	1			T26	31		T1	2819		T11	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	202122	1			T26	31		T1	2830		T11	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	4657752	1			T26	120		T27	461		T28	350
bins_for_gpio_bits[9]	auto[0]	auto[0]	6707374	1			T26	416		T27	429		T28	311
bins_for_gpio_bits[9]	auto[0]	auto[1]	202516	1			T26	22		T1	2777		T11	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	202725	1			T26	22		T1	2787		T11	6
bins_for_gpio_bits[9]	auto[1]	auto[1]	4663790	1			T26	131		T27	396		T28	281
bins_for_gpio_bits[10]	auto[0]	auto[0]	6713655	1			T26	390		T27	382		T28	308
bins_for_gpio_bits[10]	auto[0]	auto[1]	201784	1			T26	32		T1	2868		T11	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	202018	1			T26	32		T1	2885		T11	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	4658948	1			T26	137		T27	443		T28	284
bins_for_gpio_bits[11]	auto[0]	auto[0]	6712744	1			T26	361		T27	373		T28	301
bins_for_gpio_bits[11]	auto[0]	auto[1]	202250	1			T26	39		T1	2903		T11	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	202513	1			T26	39		T1	2912		T11	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	4658898	1			T26	152		T27	452		T28	291
bins_for_gpio_bits[12]	auto[0]	auto[0]	6717068	1			T26	396		T27	380		T28	302
bins_for_gpio_bits[12]	auto[0]	auto[1]	202411	1			T26	27		T1	2789		T11	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	202678	1			T26	28		T1	2800		T11	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	4654248	1			T26	140		T27	445		T28	290
bins_for_gpio_bits[13]	auto[0]	auto[0]	6712698	1			T26	357		T27	397		T28	359
bins_for_gpio_bits[13]	auto[0]	auto[1]	202164	1			T26	34		T1	2853		T11	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	202403	1			T26	34		T1	2868		T11	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	4659140	1			T26	166		T27	428		T28	233
bins_for_gpio_bits[14]	auto[0]	auto[0]	6711607	1			T26	394		T27	400		T28	292
bins_for_gpio_bits[14]	auto[0]	auto[1]	201876	1			T26	32		T1	2790		T11	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	202109	1			T26	32		T1	2799		T11	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	4660813	1			T26	133		T27	425		T28	300
bins_for_gpio_bits[15]	auto[0]	auto[0]	6728118	1			T26	367		T27	456		T28	325
bins_for_gpio_bits[15]	auto[0]	auto[1]	201964	1			T26	29		T1	2825		T11	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	202159	1			T26	30		T1	2842		T11	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	4644164	1			T26	165		T27	369		T28	267
bins_for_gpio_bits[16]	auto[0]	auto[0]	6720233	1			T26	394		T27	395		T28	285
bins_for_gpio_bits[16]	auto[0]	auto[1]	201991	1			T26	31		T1	2783		T11	4
bins_for_gpio_bits[16]	auto[1]	auto[0]	202229	1			T26	32		T1	2795		T11	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	4651952	1			T26	134		T27	430		T28	307
bins_for_gpio_bits[17]	auto[0]	auto[0]	6713813	1			T26	381		T27	450		T28	287
bins_for_gpio_bits[17]	auto[0]	auto[1]	202104	1			T26	32		T1	2829		T11	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	202342	1			T26	32		T1	2845		T11	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	4658146	1			T26	146		T27	375		T28	305
bins_for_gpio_bits[18]	auto[0]	auto[0]	6725137	1			T26	400		T27	403		T28	264
bins_for_gpio_bits[18]	auto[0]	auto[1]	202390	1			T26	30		T1	2877		T11	7
bins_for_gpio_bits[18]	auto[1]	auto[0]	202592	1			T26	30		T1	2887		T11	7
bins_for_gpio_bits[18]	auto[1]	auto[1]	4646286	1			T26	131		T27	422		T28	328
bins_for_gpio_bits[19]	auto[0]	auto[0]	6722528	1			T26	385		T27	372		T28	261
bins_for_gpio_bits[19]	auto[0]	auto[1]	201586	1			T26	30		T1	2856		T11	7
bins_for_gpio_bits[19]	auto[1]	auto[0]	201812	1			T26	30		T1	2869		T11	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	4650479	1			T26	146		T27	453		T28	331
bins_for_gpio_bits[20]	auto[0]	auto[0]	6703787	1			T26	367		T27	449		T28	309
bins_for_gpio_bits[20]	auto[0]	auto[1]	203183	1			T26	32		T1	2826		T11	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	203396	1			T26	32		T1	2836		T11	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	4666039	1			T26	160		T27	376		T28	283
bins_for_gpio_bits[21]	auto[0]	auto[0]	6718244	1			T26	389		T27	376		T28	250
bins_for_gpio_bits[21]	auto[0]	auto[1]	202076	1			T26	31		T1	2848		T11	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	202278	1			T26	31		T1	2861		T11	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	4653807	1			T26	140		T27	449		T28	342
bins_for_gpio_bits[22]	auto[0]	auto[0]	6719661	1			T26	433		T27	469		T28	273
bins_for_gpio_bits[22]	auto[0]	auto[1]	201555	1			T26	26		T1	2808		T11	6
bins_for_gpio_bits[22]	auto[1]	auto[0]	201770	1			T26	26		T1	2819		T11	6
bins_for_gpio_bits[22]	auto[1]	auto[1]	4653419	1			T26	106		T27	356		T28	319
bins_for_gpio_bits[23]	auto[0]	auto[0]	6706872	1			T26	397		T27	374		T28	337
bins_for_gpio_bits[23]	auto[0]	auto[1]	202320	1			T26	26		T1	2822		T11	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	202539	1			T26	26		T1	2834		T11	8
bins_for_gpio_bits[23]	auto[1]	auto[1]	4664674	1			T26	142		T27	451		T28	255
bins_for_gpio_bits[24]	auto[0]	auto[0]	6709138	1			T26	417		T27	454		T28	268
bins_for_gpio_bits[24]	auto[0]	auto[1]	201838	1			T26	26		T1	2774		T11	9
bins_for_gpio_bits[24]	auto[1]	auto[0]	202053	1			T26	27		T1	2785		T11	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	4663376	1			T26	121		T27	371		T28	324
bins_for_gpio_bits[25]	auto[0]	auto[0]	6711165	1			T26	373		T27	348		T28	326
bins_for_gpio_bits[25]	auto[0]	auto[1]	202112	1			T26	34		T1	2818		T11	5
bins_for_gpio_bits[25]	auto[1]	auto[0]	202316	1			T26	34		T1	2824		T11	5
bins_for_gpio_bits[25]	auto[1]	auto[1]	4660812	1			T26	150		T27	477		T28	266
bins_for_gpio_bits[26]	auto[0]	auto[0]	6704031	1			T26	371		T27	467		T28	253
bins_for_gpio_bits[26]	auto[0]	auto[1]	202249	1			T26	31		T1	2850		T11	8
bins_for_gpio_bits[26]	auto[1]	auto[0]	202497	1			T26	31		T1	2863		T11	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	4667628	1			T26	158		T27	358		T28	339
bins_for_gpio_bits[27]	auto[0]	auto[0]	6704965	1			T26	401		T27	392		T28	257
bins_for_gpio_bits[27]	auto[0]	auto[1]	202215	1			T26	26		T1	2848		T11	9
bins_for_gpio_bits[27]	auto[1]	auto[0]	202427	1			T26	26		T1	2861		T11	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	4666798	1			T26	138		T27	433		T28	335
bins_for_gpio_bits[28]	auto[0]	auto[0]	6716163	1			T26	391		T27	415		T28	266
bins_for_gpio_bits[28]	auto[0]	auto[1]	202823	1			T26	32		T1	2890		T11	5
bins_for_gpio_bits[28]	auto[1]	auto[0]	203021	1			T26	32		T1	2900		T11	5
bins_for_gpio_bits[28]	auto[1]	auto[1]	4654398	1			T26	136		T27	410		T28	326
bins_for_gpio_bits[29]	auto[0]	auto[0]	6715793	1			T26	351		T27	390		T28	280
bins_for_gpio_bits[29]	auto[0]	auto[1]	202598	1			T26	38		T1	2918		T11	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	202831	1			T26	38		T1	2932		T11	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	4655183	1			T26	164		T27	435		T28	312
bins_for_gpio_bits[30]	auto[0]	auto[0]	6720251	1			T26	405		T27	426		T28	293
bins_for_gpio_bits[30]	auto[0]	auto[1]	202418	1			T26	25		T1	2880		T11	7
bins_for_gpio_bits[30]	auto[1]	auto[0]	202630	1			T26	25		T1	2895		T11	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	4651106	1			T26	136		T27	399		T28	299
bins_for_gpio_bits[31]	auto[0]	auto[0]	6709445	1			T26	413		T27	396		T28	300
bins_for_gpio_bits[31]	auto[0]	auto[1]	202138	1			T26	27		T1	2886		T11	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	202362	1			T26	27		T1	2900		T11	5
bins_for_gpio_bits[31]	auto[1]	auto[1]	4662460	1			T26	124		T27	429		T28	292