Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7044675 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4908144 |
1 |
|
|
T29 |
6 |
|
T30 |
15 |
|
T1 |
59839 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11323639 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
629180 |
1 |
|
|
T30 |
1 |
|
T1 |
7891 |
|
T14 |
171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7027379 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4925440 |
1 |
|
|
T29 |
31 |
|
T30 |
17 |
|
T1 |
63144 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2148052 |
1 |
|
|
T29 |
25 |
|
T30 |
12 |
|
T1 |
28734 |
| auto[1] |
auto[0] |
auto[1] |
314432 |
1 |
|
|
T30 |
1 |
|
T1 |
4294 |
|
T14 |
109 |
| auto[1] |
auto[1] |
auto[0] |
2148208 |
1 |
|
|
T29 |
6 |
|
T30 |
4 |
|
T1 |
26519 |
| auto[1] |
auto[1] |
auto[1] |
314748 |
1 |
|
|
T1 |
3597 |
|
T14 |
62 |
|
T115 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |