Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7040704 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4912115 |
1 |
|
|
T29 |
27 |
|
T30 |
25 |
|
T1 |
58604 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9916897 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
2035922 |
1 |
|
|
T29 |
7 |
|
T30 |
9 |
|
T1 |
24023 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7081562 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4871257 |
1 |
|
|
T29 |
8 |
|
T30 |
17 |
|
T1 |
62475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1424650 |
1 |
|
|
T29 |
1 |
|
T30 |
5 |
|
T1 |
19631 |
| auto[1] |
auto[0] |
auto[1] |
1019413 |
1 |
|
|
T29 |
7 |
|
T30 |
3 |
|
T1 |
12834 |
| auto[1] |
auto[1] |
auto[0] |
1410685 |
1 |
|
|
T30 |
3 |
|
T1 |
18821 |
|
T14 |
176 |
| auto[1] |
auto[1] |
auto[1] |
1016509 |
1 |
|
|
T30 |
6 |
|
T1 |
11189 |
|
T14 |
200 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |