Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7048826 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4903993 |
1 |
|
|
T29 |
34 |
|
T30 |
4 |
|
T1 |
63528 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9912591 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
2040228 |
1 |
|
|
T29 |
6 |
|
T30 |
2 |
|
T1 |
22789 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7066688 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4886131 |
1 |
|
|
T29 |
6 |
|
T30 |
25 |
|
T1 |
59872 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1423374 |
1 |
|
|
T30 |
23 |
|
T1 |
18408 |
|
T14 |
116 |
| auto[1] |
auto[0] |
auto[1] |
1020855 |
1 |
|
|
T29 |
4 |
|
T30 |
2 |
|
T1 |
11127 |
| auto[1] |
auto[1] |
auto[0] |
1422529 |
1 |
|
|
T1 |
18675 |
|
T14 |
178 |
|
T115 |
34 |
| auto[1] |
auto[1] |
auto[1] |
1019373 |
1 |
|
|
T29 |
2 |
|
T1 |
11662 |
|
T14 |
159 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |