Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7035984 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4916835 |
1 |
|
|
T29 |
37 |
|
T30 |
41 |
|
T1 |
62699 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9908621 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
2044198 |
1 |
|
|
T29 |
9 |
|
T30 |
5 |
|
T1 |
23635 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7052147 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4900672 |
1 |
|
|
T29 |
10 |
|
T30 |
5 |
|
T1 |
62740 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1422889 |
1 |
|
|
T29 |
1 |
|
T1 |
19965 |
|
T14 |
226 |
| auto[1] |
auto[0] |
auto[1] |
1020210 |
1 |
|
|
T29 |
4 |
|
T1 |
11945 |
|
T14 |
206 |
| auto[1] |
auto[1] |
auto[0] |
1433585 |
1 |
|
|
T1 |
19140 |
|
T14 |
289 |
|
T115 |
19 |
| auto[1] |
auto[1] |
auto[1] |
1023988 |
1 |
|
|
T29 |
5 |
|
T30 |
5 |
|
T1 |
11690 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |