Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7053913 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4898906 |
1 |
|
|
T29 |
26 |
|
T30 |
15 |
|
T1 |
59604 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11322341 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
630478 |
1 |
|
|
T29 |
2 |
|
T30 |
1 |
|
T1 |
7781 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7023738 |
1 |
|
|
T26 |
349 |
|
T27 |
825 |
|
T28 |
592 |
| auto[1] |
4929081 |
1 |
|
|
T29 |
31 |
|
T30 |
14 |
|
T1 |
61736 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2150857 |
1 |
|
|
T29 |
19 |
|
T30 |
8 |
|
T1 |
28507 |
| auto[1] |
auto[0] |
auto[1] |
315520 |
1 |
|
|
T29 |
1 |
|
T30 |
1 |
|
T1 |
4112 |
| auto[1] |
auto[1] |
auto[0] |
2147746 |
1 |
|
|
T29 |
10 |
|
T30 |
5 |
|
T1 |
25448 |
| auto[1] |
auto[1] |
auto[1] |
314958 |
1 |
|
|
T29 |
1 |
|
T1 |
3669 |
|
T14 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |