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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
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T764 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1894573373 Jul 31 04:29:58 PM PDT 24 Jul 31 04:29:58 PM PDT 24 12084383 ps
T765 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1995967220 Jul 31 04:29:20 PM PDT 24 Jul 31 04:29:21 PM PDT 24 42680884 ps
T766 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3190632224 Jul 31 04:29:45 PM PDT 24 Jul 31 04:29:46 PM PDT 24 44589439 ps
T767 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1629336886 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:57 PM PDT 24 42295821 ps
T111 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.13808525 Jul 31 04:29:43 PM PDT 24 Jul 31 04:29:43 PM PDT 24 16819486 ps
T768 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1046335657 Jul 31 04:29:11 PM PDT 24 Jul 31 04:29:14 PM PDT 24 1808867202 ps
T769 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3081303396 Jul 31 04:29:22 PM PDT 24 Jul 31 04:29:23 PM PDT 24 26622755 ps
T112 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2895266997 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:32 PM PDT 24 113168184 ps
T770 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3603039928 Jul 31 04:29:30 PM PDT 24 Jul 31 04:29:30 PM PDT 24 86664141 ps
T771 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2327512907 Jul 31 04:24:22 PM PDT 24 Jul 31 04:24:22 PM PDT 24 13232443 ps
T772 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2173873836 Jul 31 04:24:44 PM PDT 24 Jul 31 04:24:45 PM PDT 24 22311748 ps
T773 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1884361690 Jul 31 04:29:42 PM PDT 24 Jul 31 04:29:44 PM PDT 24 247937836 ps
T774 /workspace/coverage/cover_reg_top/42.gpio_intr_test.696098643 Jul 31 04:30:30 PM PDT 24 Jul 31 04:30:31 PM PDT 24 51870495 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3371784846 Jul 31 04:29:21 PM PDT 24 Jul 31 04:29:21 PM PDT 24 228914887 ps
T776 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1640322624 Jul 31 04:29:27 PM PDT 24 Jul 31 04:29:28 PM PDT 24 32651637 ps
T777 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.209620543 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:59 PM PDT 24 364418597 ps
T778 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1130381804 Jul 31 04:20:38 PM PDT 24 Jul 31 04:20:39 PM PDT 24 83661826 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.276045919 Jul 31 04:23:48 PM PDT 24 Jul 31 04:23:48 PM PDT 24 19957273 ps
T780 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1201307392 Jul 31 04:30:00 PM PDT 24 Jul 31 04:30:01 PM PDT 24 11438120 ps
T113 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3798882941 Jul 31 04:29:58 PM PDT 24 Jul 31 04:29:59 PM PDT 24 91269312 ps
T781 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1625727703 Jul 31 04:29:20 PM PDT 24 Jul 31 04:29:21 PM PDT 24 13632367 ps
T782 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2924385316 Jul 31 04:29:45 PM PDT 24 Jul 31 04:29:46 PM PDT 24 31480407 ps
T783 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1029181752 Jul 31 04:29:49 PM PDT 24 Jul 31 04:29:51 PM PDT 24 291991885 ps
T784 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3968666309 Jul 31 04:29:20 PM PDT 24 Jul 31 04:29:23 PM PDT 24 145944704 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3046876754 Jul 31 04:29:31 PM PDT 24 Jul 31 04:29:32 PM PDT 24 47407777 ps
T786 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3135585968 Jul 31 04:25:23 PM PDT 24 Jul 31 04:25:24 PM PDT 24 222323566 ps
T51 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.388627821 Jul 31 04:21:45 PM PDT 24 Jul 31 04:21:46 PM PDT 24 139405543 ps
T787 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3279761853 Jul 31 04:25:08 PM PDT 24 Jul 31 04:25:09 PM PDT 24 55382876 ps
T95 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.335348054 Jul 31 04:21:40 PM PDT 24 Jul 31 04:21:41 PM PDT 24 35504428 ps
T788 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2940264652 Jul 31 04:30:01 PM PDT 24 Jul 31 04:30:01 PM PDT 24 148401866 ps
T789 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3527062998 Jul 31 04:20:52 PM PDT 24 Jul 31 04:20:54 PM PDT 24 455602347 ps
T790 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.626617825 Jul 31 04:29:57 PM PDT 24 Jul 31 04:29:59 PM PDT 24 293208335 ps
T791 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1085997769 Jul 31 04:29:45 PM PDT 24 Jul 31 04:29:47 PM PDT 24 762662916 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3519073252 Jul 31 04:25:38 PM PDT 24 Jul 31 04:25:40 PM PDT 24 59748313 ps
T793 /workspace/coverage/cover_reg_top/40.gpio_intr_test.495226638 Jul 31 04:30:10 PM PDT 24 Jul 31 04:30:11 PM PDT 24 12007022 ps
T794 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1063896149 Jul 31 04:29:57 PM PDT 24 Jul 31 04:29:58 PM PDT 24 14268201 ps
T795 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.5009308 Jul 31 04:23:48 PM PDT 24 Jul 31 04:23:49 PM PDT 24 77037441 ps
T796 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1580102117 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:58 PM PDT 24 36069834 ps
T797 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1190175823 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:57 PM PDT 24 35647765 ps
T798 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2600892840 Jul 31 04:29:57 PM PDT 24 Jul 31 04:29:58 PM PDT 24 103439838 ps
T799 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1710823610 Jul 31 04:21:59 PM PDT 24 Jul 31 04:22:00 PM PDT 24 91709785 ps
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2007995874 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:32 PM PDT 24 43728770 ps
T800 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1739803906 Jul 31 04:29:34 PM PDT 24 Jul 31 04:29:35 PM PDT 24 74827162 ps
T801 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1142469554 Jul 31 04:29:43 PM PDT 24 Jul 31 04:29:44 PM PDT 24 36943428 ps
T802 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1819147750 Jul 31 04:25:23 PM PDT 24 Jul 31 04:25:24 PM PDT 24 12559847 ps
T803 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4237222371 Jul 31 04:29:17 PM PDT 24 Jul 31 04:29:18 PM PDT 24 134630791 ps
T804 /workspace/coverage/cover_reg_top/17.gpio_intr_test.4100025166 Jul 31 04:29:50 PM PDT 24 Jul 31 04:29:51 PM PDT 24 21498519 ps
T805 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.590236256 Jul 31 04:29:33 PM PDT 24 Jul 31 04:29:34 PM PDT 24 328463746 ps
T806 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3617724781 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:59 PM PDT 24 66980614 ps
T807 /workspace/coverage/cover_reg_top/36.gpio_intr_test.389059955 Jul 31 04:30:39 PM PDT 24 Jul 31 04:30:40 PM PDT 24 31741873 ps
T808 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1366384917 Jul 31 04:29:29 PM PDT 24 Jul 31 04:29:31 PM PDT 24 121052348 ps
T809 /workspace/coverage/cover_reg_top/5.gpio_intr_test.645320855 Jul 31 04:21:48 PM PDT 24 Jul 31 04:21:49 PM PDT 24 14640912 ps
T810 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.228977789 Jul 31 04:29:20 PM PDT 24 Jul 31 04:29:22 PM PDT 24 238001065 ps
T97 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1905820864 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:57 PM PDT 24 106679263 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3507389637 Jul 31 04:29:50 PM PDT 24 Jul 31 04:29:50 PM PDT 24 26302905 ps
T812 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.667030907 Jul 31 04:29:36 PM PDT 24 Jul 31 04:29:37 PM PDT 24 232484656 ps
T98 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2438661194 Jul 31 04:24:40 PM PDT 24 Jul 31 04:24:41 PM PDT 24 25233056 ps
T813 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1879727142 Jul 31 04:23:32 PM PDT 24 Jul 31 04:23:35 PM PDT 24 56775591 ps
T814 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1618996748 Jul 31 04:29:29 PM PDT 24 Jul 31 04:29:30 PM PDT 24 22076412 ps
T103 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1633965962 Jul 31 04:29:41 PM PDT 24 Jul 31 04:29:42 PM PDT 24 29614007 ps
T815 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1898943199 Jul 31 04:29:35 PM PDT 24 Jul 31 04:29:36 PM PDT 24 44824260 ps
T816 /workspace/coverage/cover_reg_top/18.gpio_intr_test.912549223 Jul 31 04:29:59 PM PDT 24 Jul 31 04:30:00 PM PDT 24 15961433 ps
T99 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.978238111 Jul 31 04:29:42 PM PDT 24 Jul 31 04:29:43 PM PDT 24 22567913 ps
T817 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3808860728 Jul 31 04:29:49 PM PDT 24 Jul 31 04:29:50 PM PDT 24 35078853 ps
T818 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3493081795 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:08 PM PDT 24 81703611 ps
T100 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3854836955 Jul 31 04:29:20 PM PDT 24 Jul 31 04:29:21 PM PDT 24 56354272 ps
T819 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1315545201 Jul 31 04:29:25 PM PDT 24 Jul 31 04:29:27 PM PDT 24 58537245 ps
T820 /workspace/coverage/cover_reg_top/47.gpio_intr_test.603736127 Jul 31 04:30:12 PM PDT 24 Jul 31 04:30:13 PM PDT 24 30168609 ps
T821 /workspace/coverage/cover_reg_top/48.gpio_intr_test.165708068 Jul 31 04:30:01 PM PDT 24 Jul 31 04:30:01 PM PDT 24 16506673 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2670095970 Jul 31 04:25:24 PM PDT 24 Jul 31 04:25:25 PM PDT 24 27979646 ps
T823 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1898747977 Jul 31 04:29:48 PM PDT 24 Jul 31 04:29:49 PM PDT 24 38048697 ps
T824 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1448602692 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:34 PM PDT 24 101970279 ps
T825 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4116685384 Jul 31 04:23:38 PM PDT 24 Jul 31 04:23:39 PM PDT 24 49339116 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1955741815 Jul 31 04:29:20 PM PDT 24 Jul 31 04:29:21 PM PDT 24 177725862 ps
T827 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1599058969 Jul 31 04:25:25 PM PDT 24 Jul 31 04:25:27 PM PDT 24 37322566 ps
T101 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.525749022 Jul 31 04:24:40 PM PDT 24 Jul 31 04:24:41 PM PDT 24 213181254 ps
T828 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3175408158 Jul 31 04:29:24 PM PDT 24 Jul 31 04:29:25 PM PDT 24 40564191 ps
T102 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1079458240 Jul 31 04:29:50 PM PDT 24 Jul 31 04:29:50 PM PDT 24 22662485 ps
T829 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3667577329 Jul 31 04:25:08 PM PDT 24 Jul 31 04:25:09 PM PDT 24 35387800 ps
T830 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3436923119 Jul 31 04:30:06 PM PDT 24 Jul 31 04:30:07 PM PDT 24 18798549 ps
T831 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2290654536 Jul 31 04:29:58 PM PDT 24 Jul 31 04:29:59 PM PDT 24 13724666 ps
T832 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.288680470 Jul 31 04:29:44 PM PDT 24 Jul 31 04:29:46 PM PDT 24 310968160 ps
T833 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2182884410 Jul 31 04:29:21 PM PDT 24 Jul 31 04:29:21 PM PDT 24 63370316 ps
T834 /workspace/coverage/cover_reg_top/32.gpio_intr_test.602521308 Jul 31 04:30:01 PM PDT 24 Jul 31 04:30:02 PM PDT 24 11430195 ps
T835 /workspace/coverage/cover_reg_top/35.gpio_intr_test.633464405 Jul 31 04:30:40 PM PDT 24 Jul 31 04:30:40 PM PDT 24 249262834 ps
T836 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3402812272 Jul 31 04:29:49 PM PDT 24 Jul 31 04:29:50 PM PDT 24 131029878 ps
T837 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2743949084 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:56 PM PDT 24 12784952 ps
T838 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1127608229 Jul 31 04:29:56 PM PDT 24 Jul 31 04:29:57 PM PDT 24 17606498 ps
T839 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3378983914 Jul 31 04:24:54 PM PDT 24 Jul 31 04:24:55 PM PDT 24 44996360 ps
T840 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3424945890 Jul 31 04:29:47 PM PDT 24 Jul 31 04:29:48 PM PDT 24 25986991 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1121585292 Jul 31 04:24:21 PM PDT 24 Jul 31 04:24:22 PM PDT 24 64071288 ps
T842 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1078797935 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:58 PM PDT 24 262320924 ps
T843 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3427146978 Jul 31 04:30:10 PM PDT 24 Jul 31 04:30:11 PM PDT 24 48693707 ps
T844 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.286380479 Jul 31 04:30:19 PM PDT 24 Jul 31 04:30:20 PM PDT 24 41720668 ps
T845 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2321275956 Jul 31 04:20:47 PM PDT 24 Jul 31 04:20:49 PM PDT 24 212327590 ps
T846 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1361798617 Jul 31 04:30:15 PM PDT 24 Jul 31 04:30:17 PM PDT 24 270047828 ps
T847 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1280762669 Jul 31 04:30:23 PM PDT 24 Jul 31 04:30:24 PM PDT 24 51783890 ps
T848 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3282050117 Jul 31 04:24:57 PM PDT 24 Jul 31 04:24:58 PM PDT 24 172289432 ps
T849 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3540401433 Jul 31 04:30:08 PM PDT 24 Jul 31 04:30:09 PM PDT 24 148016119 ps
T850 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1116172618 Jul 31 04:20:41 PM PDT 24 Jul 31 04:20:42 PM PDT 24 41284372 ps
T851 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.434856008 Jul 31 04:30:19 PM PDT 24 Jul 31 04:30:20 PM PDT 24 124730780 ps
T852 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2333234422 Jul 31 04:24:45 PM PDT 24 Jul 31 04:24:46 PM PDT 24 335116160 ps
T853 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.39224318 Jul 31 04:30:16 PM PDT 24 Jul 31 04:30:18 PM PDT 24 136910844 ps
T854 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3797691900 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:57 PM PDT 24 38501132 ps
T855 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2893613055 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:32 PM PDT 24 89711056 ps
T856 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3818449489 Jul 31 04:25:00 PM PDT 24 Jul 31 04:25:02 PM PDT 24 119818162 ps
T857 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4256213781 Jul 31 04:20:41 PM PDT 24 Jul 31 04:20:42 PM PDT 24 173558078 ps
T858 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2367358938 Jul 31 04:24:44 PM PDT 24 Jul 31 04:24:46 PM PDT 24 45508959 ps
T859 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1882981899 Jul 31 04:20:55 PM PDT 24 Jul 31 04:20:56 PM PDT 24 70138723 ps
T860 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.591748883 Jul 31 04:23:34 PM PDT 24 Jul 31 04:23:35 PM PDT 24 80014596 ps
T861 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1167930820 Jul 31 04:23:49 PM PDT 24 Jul 31 04:23:50 PM PDT 24 718157677 ps
T862 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3255765695 Jul 31 04:23:49 PM PDT 24 Jul 31 04:23:50 PM PDT 24 69878111 ps
T863 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4209773474 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:08 PM PDT 24 84639679 ps
T864 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3416364245 Jul 31 04:30:20 PM PDT 24 Jul 31 04:30:21 PM PDT 24 51859138 ps
T865 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2494397200 Jul 31 04:23:48 PM PDT 24 Jul 31 04:23:49 PM PDT 24 193062496 ps
T866 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3287736255 Jul 31 04:30:13 PM PDT 24 Jul 31 04:30:14 PM PDT 24 219933421 ps
T867 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2862285321 Jul 31 04:30:12 PM PDT 24 Jul 31 04:30:13 PM PDT 24 61925236 ps
T868 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.544444454 Jul 31 04:30:27 PM PDT 24 Jul 31 04:30:28 PM PDT 24 129320153 ps
T869 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2814314781 Jul 31 04:30:17 PM PDT 24 Jul 31 04:30:19 PM PDT 24 43639242 ps
T870 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.292214285 Jul 31 04:30:13 PM PDT 24 Jul 31 04:30:14 PM PDT 24 149467003 ps
T871 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929676785 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:08 PM PDT 24 186879847 ps
T872 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2655047849 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:33 PM PDT 24 311724068 ps
T873 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11394507 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:56 PM PDT 24 41712088 ps
T874 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1526852196 Jul 31 04:24:45 PM PDT 24 Jul 31 04:24:46 PM PDT 24 51594616 ps
T875 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3999067105 Jul 31 04:22:26 PM PDT 24 Jul 31 04:22:27 PM PDT 24 39099646 ps
T876 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.547480953 Jul 31 04:30:09 PM PDT 24 Jul 31 04:30:10 PM PDT 24 447743867 ps
T877 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1463176704 Jul 31 04:24:57 PM PDT 24 Jul 31 04:24:58 PM PDT 24 55537452 ps
T878 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3375073008 Jul 31 04:30:22 PM PDT 24 Jul 31 04:30:23 PM PDT 24 102823038 ps
T879 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1880486501 Jul 31 04:25:25 PM PDT 24 Jul 31 04:25:27 PM PDT 24 70859851 ps
T880 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3570945657 Jul 31 04:30:14 PM PDT 24 Jul 31 04:30:15 PM PDT 24 39340835 ps
T881 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3891394968 Jul 31 04:30:11 PM PDT 24 Jul 31 04:30:12 PM PDT 24 273993636 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1154922990 Jul 31 04:23:16 PM PDT 24 Jul 31 04:23:18 PM PDT 24 281076228 ps
T883 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1131848479 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:09 PM PDT 24 52996484 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123079240 Jul 31 04:30:23 PM PDT 24 Jul 31 04:30:25 PM PDT 24 51506681 ps
T885 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2164617192 Jul 31 04:30:17 PM PDT 24 Jul 31 04:30:19 PM PDT 24 237563663 ps
T886 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3942306035 Jul 31 04:22:45 PM PDT 24 Jul 31 04:22:46 PM PDT 24 290077351 ps
T887 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2483262192 Jul 31 04:25:42 PM PDT 24 Jul 31 04:25:44 PM PDT 24 50225780 ps
T888 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.468908818 Jul 31 04:30:14 PM PDT 24 Jul 31 04:30:15 PM PDT 24 565365878 ps
T889 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.527814554 Jul 31 04:30:22 PM PDT 24 Jul 31 04:30:23 PM PDT 24 91927333 ps
T890 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2396711915 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:07 PM PDT 24 26125170 ps
T891 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3991611545 Jul 31 04:25:00 PM PDT 24 Jul 31 04:25:01 PM PDT 24 66983057 ps
T892 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151986942 Jul 31 04:24:41 PM PDT 24 Jul 31 04:24:42 PM PDT 24 56447380 ps
T893 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2936783983 Jul 31 04:23:45 PM PDT 24 Jul 31 04:23:46 PM PDT 24 51436295 ps
T894 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1137943802 Jul 31 04:30:23 PM PDT 24 Jul 31 04:30:24 PM PDT 24 331246316 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2716646271 Jul 31 04:25:08 PM PDT 24 Jul 31 04:25:09 PM PDT 24 193118670 ps
T896 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1807975693 Jul 31 04:30:11 PM PDT 24 Jul 31 04:30:13 PM PDT 24 153229249 ps
T897 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2140964368 Jul 31 04:30:08 PM PDT 24 Jul 31 04:30:09 PM PDT 24 270042453 ps
T898 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2284750271 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:08 PM PDT 24 47421330 ps
T899 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2926881468 Jul 31 04:23:55 PM PDT 24 Jul 31 04:23:56 PM PDT 24 271346587 ps
T900 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193079236 Jul 31 04:30:08 PM PDT 24 Jul 31 04:30:10 PM PDT 24 276714344 ps
T901 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1730630062 Jul 31 04:30:18 PM PDT 24 Jul 31 04:30:20 PM PDT 24 138491453 ps
T902 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3984362268 Jul 31 04:24:45 PM PDT 24 Jul 31 04:24:46 PM PDT 24 47186988 ps
T903 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3482866429 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:32 PM PDT 24 103855530 ps
T904 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2323401879 Jul 31 04:30:23 PM PDT 24 Jul 31 04:30:24 PM PDT 24 101580095 ps
T905 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.655138046 Jul 31 04:30:18 PM PDT 24 Jul 31 04:30:20 PM PDT 24 296038833 ps
T906 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3608975148 Jul 31 04:30:19 PM PDT 24 Jul 31 04:30:20 PM PDT 24 63881498 ps
T907 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.729601195 Jul 31 04:23:48 PM PDT 24 Jul 31 04:23:49 PM PDT 24 57823073 ps
T908 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2530433107 Jul 31 04:30:14 PM PDT 24 Jul 31 04:30:15 PM PDT 24 280139995 ps
T909 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2371918502 Jul 31 04:25:39 PM PDT 24 Jul 31 04:25:41 PM PDT 24 337717468 ps
T910 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1019184866 Jul 31 04:25:00 PM PDT 24 Jul 31 04:25:01 PM PDT 24 253096835 ps
T911 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.171057779 Jul 31 04:30:15 PM PDT 24 Jul 31 04:30:16 PM PDT 24 112982160 ps
T912 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3492717138 Jul 31 04:21:10 PM PDT 24 Jul 31 04:21:10 PM PDT 24 88447821 ps
T913 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.157872212 Jul 31 04:30:12 PM PDT 24 Jul 31 04:30:13 PM PDT 24 54581493 ps
T914 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2961831194 Jul 31 04:30:25 PM PDT 24 Jul 31 04:30:26 PM PDT 24 38101445 ps
T915 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.856342481 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:09 PM PDT 24 88155045 ps
T916 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2616695153 Jul 31 04:30:19 PM PDT 24 Jul 31 04:30:20 PM PDT 24 147343688 ps
T917 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3483811308 Jul 31 04:25:23 PM PDT 24 Jul 31 04:25:24 PM PDT 24 126777856 ps
T918 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1803632377 Jul 31 04:22:00 PM PDT 24 Jul 31 04:22:01 PM PDT 24 544562442 ps
T919 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.57309106 Jul 31 04:23:34 PM PDT 24 Jul 31 04:23:35 PM PDT 24 41563234 ps
T920 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3472801039 Jul 31 04:30:21 PM PDT 24 Jul 31 04:30:22 PM PDT 24 55119722 ps
T921 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3563614207 Jul 31 04:30:30 PM PDT 24 Jul 31 04:30:31 PM PDT 24 414894446 ps
T922 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032512092 Jul 31 04:30:17 PM PDT 24 Jul 31 04:30:19 PM PDT 24 25276926 ps
T923 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.97532448 Jul 31 04:25:00 PM PDT 24 Jul 31 04:25:01 PM PDT 24 51454172 ps
T924 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2853786493 Jul 31 04:23:48 PM PDT 24 Jul 31 04:23:49 PM PDT 24 161632442 ps
T925 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3966288609 Jul 31 04:30:08 PM PDT 24 Jul 31 04:30:09 PM PDT 24 56649981 ps
T926 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.647492039 Jul 31 04:30:07 PM PDT 24 Jul 31 04:30:08 PM PDT 24 141314872 ps
T927 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3375393830 Jul 31 04:21:48 PM PDT 24 Jul 31 04:21:49 PM PDT 24 230765888 ps
T928 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.854059870 Jul 31 04:30:13 PM PDT 24 Jul 31 04:30:14 PM PDT 24 28223601 ps
T929 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.607515317 Jul 31 04:30:23 PM PDT 24 Jul 31 04:30:24 PM PDT 24 40469819 ps
T930 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3811354147 Jul 31 04:23:47 PM PDT 24 Jul 31 04:23:48 PM PDT 24 63829414 ps
T931 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1362343456 Jul 31 04:23:54 PM PDT 24 Jul 31 04:23:55 PM PDT 24 174951087 ps
T932 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1989883498 Jul 31 04:23:53 PM PDT 24 Jul 31 04:23:54 PM PDT 24 218669219 ps
T933 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3088619419 Jul 31 04:30:08 PM PDT 24 Jul 31 04:30:09 PM PDT 24 77823472 ps
T934 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2525196965 Jul 31 04:22:16 PM PDT 24 Jul 31 04:22:17 PM PDT 24 86328886 ps
T935 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394946423 Jul 31 04:23:23 PM PDT 24 Jul 31 04:23:24 PM PDT 24 174712155 ps
T936 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2429823152 Jul 31 04:23:11 PM PDT 24 Jul 31 04:23:12 PM PDT 24 134043806 ps
T937 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.180493852 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:57 PM PDT 24 109207526 ps
T938 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3293488130 Jul 31 04:30:25 PM PDT 24 Jul 31 04:30:27 PM PDT 24 79523345 ps
T939 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.978154486 Jul 31 04:30:23 PM PDT 24 Jul 31 04:30:25 PM PDT 24 181387809 ps
T940 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2975261051 Jul 31 04:23:48 PM PDT 24 Jul 31 04:23:49 PM PDT 24 50045661 ps
T941 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1584108953 Jul 31 04:21:33 PM PDT 24 Jul 31 04:21:34 PM PDT 24 179443107 ps
T942 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225733939 Jul 31 04:24:41 PM PDT 24 Jul 31 04:24:43 PM PDT 24 207165875 ps

Test location /workspace/coverage/default/38.gpio_stress_all.2160829101
Short name T1
Test name
Test status
Simulation time 326162781074 ps
CPU time 240.7 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:42:01 PM PDT 24
Peak memory 198684 kb
Host smart-b1d96d19-7913-4cb9-8266-01d3ef734001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160829101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2160829101
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.944404311
Short name T13
Test name
Test status
Simulation time 121036514 ps
CPU time 1.38 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:28 PM PDT 24
Peak memory 196716 kb
Host smart-da1c3058-ed7b-4558-a0ff-4900a8c90208
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944404311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.944404311
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.226165177
Short name T65
Test name
Test status
Simulation time 1014850976933 ps
CPU time 2612.84 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 05:21:42 PM PDT 24
Peak memory 198732 kb
Host smart-97d1c0d7-e013-42df-ab1e-89155f4b09f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=226165177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.226165177
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1364357101
Short name T37
Test name
Test status
Simulation time 235286837 ps
CPU time 0.81 seconds
Started Jul 31 04:36:29 PM PDT 24
Finished Jul 31 04:36:30 PM PDT 24
Peak memory 214228 kb
Host smart-ea5bc851-ba0e-4920-a6eb-3546f7b5e803
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364357101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1364357101
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2945659999
Short name T89
Test name
Test status
Simulation time 28977509 ps
CPU time 0.62 seconds
Started Jul 31 04:20:42 PM PDT 24
Finished Jul 31 04:20:42 PM PDT 24
Peak memory 195136 kb
Host smart-3fbbff6e-3ad7-4420-ab6b-950854e6ce28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945659999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2945659999
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2213662629
Short name T49
Test name
Test status
Simulation time 595171707 ps
CPU time 1.33 seconds
Started Jul 31 04:29:42 PM PDT 24
Finished Jul 31 04:29:44 PM PDT 24
Peak memory 198564 kb
Host smart-38c373ac-c10d-4b81-8585-8cba59784b39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213662629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2213662629
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4006280590
Short name T42
Test name
Test status
Simulation time 40927025 ps
CPU time 0.55 seconds
Started Jul 31 04:36:49 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 194320 kb
Host smart-f8cc6d32-0182-43ce-83dc-bf12486e0ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006280590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4006280590
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.218595825
Short name T108
Test name
Test status
Simulation time 23240230 ps
CPU time 0.61 seconds
Started Jul 31 04:29:35 PM PDT 24
Finished Jul 31 04:29:36 PM PDT 24
Peak memory 195896 kb
Host smart-2eae4edd-edd5-45f0-974e-76a2fc7ed29a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218595825 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.218595825
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1377147553
Short name T50
Test name
Test status
Simulation time 146528426 ps
CPU time 1.37 seconds
Started Jul 31 04:29:22 PM PDT 24
Finished Jul 31 04:29:24 PM PDT 24
Peak memory 198584 kb
Host smart-abd81057-b02a-4fc8-b023-a6206d4a00ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377147553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1377147553
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.590236256
Short name T805
Test name
Test status
Simulation time 328463746 ps
CPU time 1.33 seconds
Started Jul 31 04:29:33 PM PDT 24
Finished Jul 31 04:29:34 PM PDT 24
Peak memory 198512 kb
Host smart-9ec7a8a2-d485-4f7d-b1b7-bdc2b7a2d638
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590236256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.590236256
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.335348054
Short name T95
Test name
Test status
Simulation time 35504428 ps
CPU time 0.92 seconds
Started Jul 31 04:21:40 PM PDT 24
Finished Jul 31 04:21:41 PM PDT 24
Peak memory 198304 kb
Host smart-f95f65b5-300f-4ff0-ae16-e02a62708e6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335348054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.335348054
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1078797935
Short name T842
Test name
Test status
Simulation time 262320924 ps
CPU time 2.26 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 197500 kb
Host smart-0d965a37-a2c3-43ec-b76b-cc8d1149c599
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078797935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1078797935
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4274785682
Short name T84
Test name
Test status
Simulation time 145070634 ps
CPU time 0.58 seconds
Started Jul 31 04:23:38 PM PDT 24
Finished Jul 31 04:23:39 PM PDT 24
Peak memory 195072 kb
Host smart-58c21221-6c9f-4aa0-b6ae-ab63ebeb5f1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274785682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4274785682
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.4116685384
Short name T825
Test name
Test status
Simulation time 49339116 ps
CPU time 0.7 seconds
Started Jul 31 04:23:38 PM PDT 24
Finished Jul 31 04:23:39 PM PDT 24
Peak memory 196988 kb
Host smart-b38f2e0a-a761-429d-8fa8-27325c3efff6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116685384 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.4116685384
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.525749022
Short name T101
Test name
Test status
Simulation time 213181254 ps
CPU time 0.61 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 194240 kb
Host smart-28bfc64a-b920-4fe5-b61b-498b4d6b4de2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525749022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.525749022
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1539968738
Short name T760
Test name
Test status
Simulation time 45809448 ps
CPU time 0.59 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 194856 kb
Host smart-7119f322-0287-4624-9ec5-60e45f4cd9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539968738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1539968738
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.276045919
Short name T779
Test name
Test status
Simulation time 19957273 ps
CPU time 0.64 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:23:48 PM PDT 24
Peak memory 195748 kb
Host smart-f1235f54-242b-45f2-9993-cbab0e62d0df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276045919 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.276045919
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.4036653258
Short name T753
Test name
Test status
Simulation time 119218644 ps
CPU time 0.98 seconds
Started Jul 31 04:22:45 PM PDT 24
Finished Jul 31 04:22:46 PM PDT 24
Peak memory 198448 kb
Host smart-11652470-694c-4dfa-bb9e-c9c5a088f737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036653258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.4036653258
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1130381804
Short name T778
Test name
Test status
Simulation time 83661826 ps
CPU time 1.14 seconds
Started Jul 31 04:20:38 PM PDT 24
Finished Jul 31 04:20:39 PM PDT 24
Peak memory 198228 kb
Host smart-ced859a7-1550-49e2-a685-7467c03d3512
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130381804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1130381804
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3378983914
Short name T839
Test name
Test status
Simulation time 44996360 ps
CPU time 0.62 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 194856 kb
Host smart-481edc19-e192-4ac9-ba5d-883e70c8d917
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378983914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3378983914
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.956621919
Short name T745
Test name
Test status
Simulation time 375930374 ps
CPU time 1.37 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 197360 kb
Host smart-9b1ba789-2d3a-4c7a-ab17-6c5ae2b403a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956621919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.956621919
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1906141245
Short name T92
Test name
Test status
Simulation time 28892413 ps
CPU time 0.63 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 195060 kb
Host smart-7b428390-0e3f-4bc6-b4fb-9b62fa6a05ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906141245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1906141245
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1599058969
Short name T827
Test name
Test status
Simulation time 37322566 ps
CPU time 0.98 seconds
Started Jul 31 04:25:25 PM PDT 24
Finished Jul 31 04:25:27 PM PDT 24
Peak memory 196776 kb
Host smart-db1e5d1e-cc2e-4900-9054-2ac82dc1674c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599058969 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1599058969
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2866474564
Short name T763
Test name
Test status
Simulation time 13826000 ps
CPU time 0.6 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 195320 kb
Host smart-c2bfa914-7426-4dc0-bd49-360d92a21305
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866474564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2866474564
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.226387225
Short name T751
Test name
Test status
Simulation time 14907724 ps
CPU time 0.66 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 192648 kb
Host smart-04b972c0-4f25-4745-b0ed-c638201ea832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226387225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.226387225
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1710823610
Short name T799
Test name
Test status
Simulation time 91709785 ps
CPU time 0.76 seconds
Started Jul 31 04:21:59 PM PDT 24
Finished Jul 31 04:22:00 PM PDT 24
Peak memory 196448 kb
Host smart-ca1f59b9-4ecd-441e-939e-a3b57ddde6be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710823610 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1710823610
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2865821391
Short name T727
Test name
Test status
Simulation time 126494570 ps
CPU time 1.4 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 198592 kb
Host smart-5c21f68e-c29f-480f-a498-0ef81b1baab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865821391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2865821391
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3198596943
Short name T43
Test name
Test status
Simulation time 193576273 ps
CPU time 0.82 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 197696 kb
Host smart-aa4b895e-2b23-48ef-8d75-9f074728156f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198596943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3198596943
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1371445594
Short name T749
Test name
Test status
Simulation time 72263168 ps
CPU time 0.73 seconds
Started Jul 31 04:29:25 PM PDT 24
Finished Jul 31 04:29:26 PM PDT 24
Peak memory 198540 kb
Host smart-00acc86e-fdca-424c-b7f2-f650d4397f7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371445594 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1371445594
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1990049861
Short name T93
Test name
Test status
Simulation time 42447323 ps
CPU time 0.58 seconds
Started Jul 31 04:29:25 PM PDT 24
Finished Jul 31 04:29:26 PM PDT 24
Peak memory 195392 kb
Host smart-e831eadb-0394-423f-b6a0-49fa093eb08d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990049861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1990049861
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3175408158
Short name T828
Test name
Test status
Simulation time 40564191 ps
CPU time 0.56 seconds
Started Jul 31 04:29:24 PM PDT 24
Finished Jul 31 04:29:25 PM PDT 24
Peak memory 194280 kb
Host smart-9072e0b5-6aab-4054-b5d5-855194a7a086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175408158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3175408158
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1640322624
Short name T776
Test name
Test status
Simulation time 32651637 ps
CPU time 0.72 seconds
Started Jul 31 04:29:27 PM PDT 24
Finished Jul 31 04:29:28 PM PDT 24
Peak memory 196540 kb
Host smart-ea07e21d-579a-4d5b-bd35-681ad937b73d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640322624 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1640322624
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1315545201
Short name T819
Test name
Test status
Simulation time 58537245 ps
CPU time 1.42 seconds
Started Jul 31 04:29:25 PM PDT 24
Finished Jul 31 04:29:27 PM PDT 24
Peak memory 198716 kb
Host smart-c04dda63-0126-4141-af0c-e76fde442612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315545201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1315545201
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3278452316
Short name T739
Test name
Test status
Simulation time 52576196 ps
CPU time 1.25 seconds
Started Jul 31 04:29:31 PM PDT 24
Finished Jul 31 04:29:32 PM PDT 24
Peak memory 198636 kb
Host smart-969f45eb-5556-4aa1-8db5-b2a81970c0ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278452316 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3278452316
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1618996748
Short name T814
Test name
Test status
Simulation time 22076412 ps
CPU time 0.6 seconds
Started Jul 31 04:29:29 PM PDT 24
Finished Jul 31 04:29:30 PM PDT 24
Peak memory 194576 kb
Host smart-815e3aa4-ae64-42dd-8bff-be57a26d69c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618996748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1618996748
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2169854687
Short name T757
Test name
Test status
Simulation time 48720577 ps
CPU time 0.54 seconds
Started Jul 31 04:29:31 PM PDT 24
Finished Jul 31 04:29:32 PM PDT 24
Peak memory 194288 kb
Host smart-c44f6590-ffbc-468c-9471-b58919e02998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169854687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2169854687
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3603039928
Short name T770
Test name
Test status
Simulation time 86664141 ps
CPU time 0.7 seconds
Started Jul 31 04:29:30 PM PDT 24
Finished Jul 31 04:29:30 PM PDT 24
Peak memory 195544 kb
Host smart-57723cb0-da07-4e46-ba31-c6b94b227bfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603039928 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3603039928
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.626617825
Short name T790
Test name
Test status
Simulation time 293208335 ps
CPU time 1.57 seconds
Started Jul 31 04:29:57 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 198660 kb
Host smart-b54fb882-61a3-4366-8494-b5725d991d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626617825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.626617825
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1085997769
Short name T791
Test name
Test status
Simulation time 762662916 ps
CPU time 1.28 seconds
Started Jul 31 04:29:45 PM PDT 24
Finished Jul 31 04:29:47 PM PDT 24
Peak memory 198624 kb
Host smart-46e74ac6-0156-4dd6-84e4-3ff3fa88d1fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085997769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1085997769
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3046876754
Short name T785
Test name
Test status
Simulation time 47407777 ps
CPU time 0.7 seconds
Started Jul 31 04:29:31 PM PDT 24
Finished Jul 31 04:29:32 PM PDT 24
Peak memory 192068 kb
Host smart-ed9efefa-7ee1-4d00-a8aa-1aceb5cf3e2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046876754 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3046876754
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1905820864
Short name T97
Test name
Test status
Simulation time 106679263 ps
CPU time 0.58 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 195800 kb
Host smart-7bb84aac-8407-412a-b9fa-af1ad7ac3e8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905820864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1905820864
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3816631698
Short name T726
Test name
Test status
Simulation time 14013093 ps
CPU time 0.57 seconds
Started Jul 31 04:29:36 PM PDT 24
Finished Jul 31 04:29:36 PM PDT 24
Peak memory 194932 kb
Host smart-5563a68f-aaab-4c7f-a710-0a81c2e93c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816631698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3816631698
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1739803906
Short name T800
Test name
Test status
Simulation time 74827162 ps
CPU time 0.63 seconds
Started Jul 31 04:29:34 PM PDT 24
Finished Jul 31 04:29:35 PM PDT 24
Peak memory 195236 kb
Host smart-8d72016f-e78b-4989-bcf6-9ea7f8651579
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739803906 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1739803906
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1366384917
Short name T808
Test name
Test status
Simulation time 121052348 ps
CPU time 2.07 seconds
Started Jul 31 04:29:29 PM PDT 24
Finished Jul 31 04:29:31 PM PDT 24
Peak memory 198656 kb
Host smart-8809e698-579b-4023-9e3e-48d85d69e326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366384917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1366384917
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1366829056
Short name T33
Test name
Test status
Simulation time 805766894 ps
CPU time 1.25 seconds
Started Jul 31 04:29:39 PM PDT 24
Finished Jul 31 04:29:41 PM PDT 24
Peak memory 198580 kb
Host smart-a7622f38-bb22-4b0c-a8bb-a7ee1406d584
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366829056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1366829056
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.667030907
Short name T812
Test name
Test status
Simulation time 232484656 ps
CPU time 0.96 seconds
Started Jul 31 04:29:36 PM PDT 24
Finished Jul 31 04:29:37 PM PDT 24
Peak memory 198436 kb
Host smart-c644009c-e3ed-4298-930f-73a1cf5dd3e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667030907 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.667030907
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1633965962
Short name T103
Test name
Test status
Simulation time 29614007 ps
CPU time 0.6 seconds
Started Jul 31 04:29:41 PM PDT 24
Finished Jul 31 04:29:42 PM PDT 24
Peak memory 195252 kb
Host smart-f0da7b5e-5d63-4457-8160-3d749f2d0816
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633965962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1633965962
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3190632224
Short name T766
Test name
Test status
Simulation time 44589439 ps
CPU time 0.55 seconds
Started Jul 31 04:29:45 PM PDT 24
Finished Jul 31 04:29:46 PM PDT 24
Peak memory 194212 kb
Host smart-97b550ab-5ed7-45e8-9555-ea28989b0291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190632224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3190632224
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1884361690
Short name T773
Test name
Test status
Simulation time 247937836 ps
CPU time 1.46 seconds
Started Jul 31 04:29:42 PM PDT 24
Finished Jul 31 04:29:44 PM PDT 24
Peak memory 198708 kb
Host smart-bb6a4187-9f63-4055-87a2-d9c272917af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884361690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1884361690
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1898943199
Short name T815
Test name
Test status
Simulation time 44824260 ps
CPU time 0.84 seconds
Started Jul 31 04:29:35 PM PDT 24
Finished Jul 31 04:29:36 PM PDT 24
Peak memory 198372 kb
Host smart-13f70714-0748-42dd-879f-4e3792dca90f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898943199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1898943199
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3738946996
Short name T720
Test name
Test status
Simulation time 67714022 ps
CPU time 0.88 seconds
Started Jul 31 04:29:44 PM PDT 24
Finished Jul 31 04:29:45 PM PDT 24
Peak memory 198464 kb
Host smart-27a26fa6-c10c-4d19-ab03-bc0feba34d19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738946996 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3738946996
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.978238111
Short name T99
Test name
Test status
Simulation time 22567913 ps
CPU time 0.57 seconds
Started Jul 31 04:29:42 PM PDT 24
Finished Jul 31 04:29:43 PM PDT 24
Peak memory 196096 kb
Host smart-0b8f8879-be86-46f6-92bc-66f7eee4282f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978238111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.978238111
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1142469554
Short name T801
Test name
Test status
Simulation time 36943428 ps
CPU time 0.59 seconds
Started Jul 31 04:29:43 PM PDT 24
Finished Jul 31 04:29:44 PM PDT 24
Peak memory 194400 kb
Host smart-a637d8cb-d40b-4866-b9d7-2cf4e635c433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142469554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1142469554
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.13808525
Short name T111
Test name
Test status
Simulation time 16819486 ps
CPU time 0.68 seconds
Started Jul 31 04:29:43 PM PDT 24
Finished Jul 31 04:29:43 PM PDT 24
Peak memory 195108 kb
Host smart-b9c69d97-aa93-4d07-bf3a-8bc2166f1f48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13808525 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.gpio_same_csr_outstanding.13808525
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.288680470
Short name T832
Test name
Test status
Simulation time 310968160 ps
CPU time 1.52 seconds
Started Jul 31 04:29:44 PM PDT 24
Finished Jul 31 04:29:46 PM PDT 24
Peak memory 198564 kb
Host smart-fad3da19-8339-4549-b93c-d989c87b6bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288680470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.288680470
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3558049197
Short name T46
Test name
Test status
Simulation time 417873492 ps
CPU time 1.38 seconds
Started Jul 31 04:29:43 PM PDT 24
Finished Jul 31 04:29:45 PM PDT 24
Peak memory 198488 kb
Host smart-b4622e1a-429e-4183-86e5-b503612396fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558049197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3558049197
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2924385316
Short name T782
Test name
Test status
Simulation time 31480407 ps
CPU time 0.84 seconds
Started Jul 31 04:29:45 PM PDT 24
Finished Jul 31 04:29:46 PM PDT 24
Peak memory 198404 kb
Host smart-89d5a38c-3149-4858-8256-dff8621d652a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924385316 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2924385316
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.985698442
Short name T86
Test name
Test status
Simulation time 19365940 ps
CPU time 0.59 seconds
Started Jul 31 04:29:47 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 195424 kb
Host smart-53238f65-b22d-43a7-a5ae-a72c10df2e30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985698442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.985698442
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.945346579
Short name T729
Test name
Test status
Simulation time 16028590 ps
CPU time 0.59 seconds
Started Jul 31 04:29:43 PM PDT 24
Finished Jul 31 04:29:44 PM PDT 24
Peak memory 194376 kb
Host smart-037cd945-00d2-4ecc-951a-0c57d612996a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945346579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.945346579
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1898747977
Short name T823
Test name
Test status
Simulation time 38048697 ps
CPU time 0.59 seconds
Started Jul 31 04:29:48 PM PDT 24
Finished Jul 31 04:29:49 PM PDT 24
Peak memory 196044 kb
Host smart-c1b3505c-688d-41bd-88bc-8ea69599dd63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898747977 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1898747977
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.788610191
Short name T728
Test name
Test status
Simulation time 194427051 ps
CPU time 3.16 seconds
Started Jul 31 04:29:43 PM PDT 24
Finished Jul 31 04:29:46 PM PDT 24
Peak memory 198580 kb
Host smart-4f05d0fb-733a-4af7-a291-3b7195d6ef07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788610191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.788610191
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1040359771
Short name T740
Test name
Test status
Simulation time 32636112 ps
CPU time 0.67 seconds
Started Jul 31 04:29:52 PM PDT 24
Finished Jul 31 04:29:53 PM PDT 24
Peak memory 197832 kb
Host smart-c4a3ae8e-9015-4d25-b71f-484fcdc9923d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040359771 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1040359771
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2477204914
Short name T88
Test name
Test status
Simulation time 31647462 ps
CPU time 0.61 seconds
Started Jul 31 04:29:50 PM PDT 24
Finished Jul 31 04:29:51 PM PDT 24
Peak memory 196012 kb
Host smart-97d89f62-5bbd-4e52-9481-c64ddf7d2d2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477204914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2477204914
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3507389637
Short name T811
Test name
Test status
Simulation time 26302905 ps
CPU time 0.55 seconds
Started Jul 31 04:29:50 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 194292 kb
Host smart-7b1eda4e-218f-461d-a744-5f169ad51dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507389637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3507389637
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.125778341
Short name T110
Test name
Test status
Simulation time 34519820 ps
CPU time 0.61 seconds
Started Jul 31 04:29:49 PM PDT 24
Finished Jul 31 04:29:49 PM PDT 24
Peak memory 195500 kb
Host smart-2f1600b3-1984-4795-b7b8-db331f37dffd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125778341 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.125778341
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1029181752
Short name T783
Test name
Test status
Simulation time 291991885 ps
CPU time 2.06 seconds
Started Jul 31 04:29:49 PM PDT 24
Finished Jul 31 04:29:51 PM PDT 24
Peak memory 198596 kb
Host smart-7b064d11-82d9-464c-8693-c59edb0912f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029181752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1029181752
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.729168310
Short name T34
Test name
Test status
Simulation time 134020471 ps
CPU time 0.84 seconds
Started Jul 31 04:29:49 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 197828 kb
Host smart-90316d94-00c8-49fa-ba5e-623ca2270334
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729168310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.729168310
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2123123740
Short name T722
Test name
Test status
Simulation time 26193756 ps
CPU time 0.93 seconds
Started Jul 31 04:29:48 PM PDT 24
Finished Jul 31 04:29:49 PM PDT 24
Peak memory 198476 kb
Host smart-4b15b56a-fb2d-49f9-815b-f24499e1189c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123123740 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2123123740
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1079458240
Short name T102
Test name
Test status
Simulation time 22662485 ps
CPU time 0.56 seconds
Started Jul 31 04:29:50 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 195472 kb
Host smart-1809aaba-92fd-45da-ba22-1dcb9a2c501b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079458240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1079458240
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.4100025166
Short name T804
Test name
Test status
Simulation time 21498519 ps
CPU time 0.6 seconds
Started Jul 31 04:29:50 PM PDT 24
Finished Jul 31 04:29:51 PM PDT 24
Peak memory 194420 kb
Host smart-70371302-d641-4ff7-ad57-7fc543e5466e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100025166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4100025166
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3402812272
Short name T836
Test name
Test status
Simulation time 131029878 ps
CPU time 0.8 seconds
Started Jul 31 04:29:49 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 196916 kb
Host smart-2b000b10-d868-464c-a285-ce070269aa45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402812272 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3402812272
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3808860728
Short name T817
Test name
Test status
Simulation time 35078853 ps
CPU time 1 seconds
Started Jul 31 04:29:49 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 198456 kb
Host smart-4d91a274-3b18-47d6-9f71-5dd1f9b21692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808860728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3808860728
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2536968592
Short name T114
Test name
Test status
Simulation time 80468507 ps
CPU time 0.86 seconds
Started Jul 31 04:29:51 PM PDT 24
Finished Jul 31 04:29:52 PM PDT 24
Peak memory 197724 kb
Host smart-97f84454-f576-4dd1-9196-04970d121157
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536968592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2536968592
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2600892840
Short name T798
Test name
Test status
Simulation time 103439838 ps
CPU time 1.3 seconds
Started Jul 31 04:29:57 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 198612 kb
Host smart-2ad9846e-3926-4a74-9668-e965a5f0618d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600892840 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2600892840
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1629336886
Short name T767
Test name
Test status
Simulation time 42295821 ps
CPU time 0.57 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 195168 kb
Host smart-3b38bf06-2083-4c19-a631-90219a23d42b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629336886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1629336886
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.912549223
Short name T816
Test name
Test status
Simulation time 15961433 ps
CPU time 0.56 seconds
Started Jul 31 04:29:59 PM PDT 24
Finished Jul 31 04:30:00 PM PDT 24
Peak memory 194288 kb
Host smart-bc170bb4-4365-4ab7-b964-136ed03fb001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912549223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.912549223
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3363527566
Short name T104
Test name
Test status
Simulation time 17344512 ps
CPU time 0.78 seconds
Started Jul 31 04:29:57 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 197364 kb
Host smart-9c8548ed-456b-47e5-b7c1-c5b9aed1f7b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363527566 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3363527566
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3617724781
Short name T806
Test name
Test status
Simulation time 66980614 ps
CPU time 1.48 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 198564 kb
Host smart-031a5114-08d9-4dc9-83f1-01e743a8822e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617724781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3617724781
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3798882941
Short name T113
Test name
Test status
Simulation time 91269312 ps
CPU time 0.84 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 197656 kb
Host smart-eb605e56-ede8-4843-b671-0a283071f9ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798882941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3798882941
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2812936778
Short name T744
Test name
Test status
Simulation time 26271035 ps
CPU time 0.82 seconds
Started Jul 31 04:29:57 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 198456 kb
Host smart-bc4dbafe-5084-4ff8-a309-4b7e17dafeba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812936778 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2812936778
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.474266829
Short name T750
Test name
Test status
Simulation time 72608858 ps
CPU time 0.55 seconds
Started Jul 31 04:29:59 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 195852 kb
Host smart-fabab4da-3013-42a2-8215-010803f42e25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474266829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.474266829
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1063896149
Short name T794
Test name
Test status
Simulation time 14268201 ps
CPU time 0.57 seconds
Started Jul 31 04:29:57 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 194944 kb
Host smart-9c4e1a32-d4c2-4219-8c10-bd7bc3b91f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063896149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1063896149
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1127608229
Short name T838
Test name
Test status
Simulation time 17606498 ps
CPU time 0.73 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 196608 kb
Host smart-4eedd216-6189-4214-838e-e5bd52c5cba2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127608229 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1127608229
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.209620543
Short name T777
Test name
Test status
Simulation time 364418597 ps
CPU time 1.81 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 198620 kb
Host smart-6c5a19b5-5b03-4713-925a-d64be0debfd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209620543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.209620543
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.924802803
Short name T36
Test name
Test status
Simulation time 329413564 ps
CPU time 1.32 seconds
Started Jul 31 04:29:57 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 198500 kb
Host smart-e58940a0-f2a9-4f02-b881-3962bd42305e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924802803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.924802803
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.552147478
Short name T85
Test name
Test status
Simulation time 49402546 ps
CPU time 0.8 seconds
Started Jul 31 04:23:46 PM PDT 24
Finished Jul 31 04:23:47 PM PDT 24
Peak memory 197140 kb
Host smart-a8249365-7871-4d13-bab8-e5632c06fb74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552147478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.552147478
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3519073252
Short name T792
Test name
Test status
Simulation time 59748313 ps
CPU time 1.32 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 198428 kb
Host smart-ec18e2dd-b2e4-4ea4-8b04-e0d478e1a9d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519073252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3519073252
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.209041179
Short name T743
Test name
Test status
Simulation time 49434075 ps
CPU time 0.81 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:23:48 PM PDT 24
Peak memory 198396 kb
Host smart-9e688e51-6aab-4417-9e8b-2ce95ac93289
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209041179 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.209041179
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2007995874
Short name T96
Test name
Test status
Simulation time 43728770 ps
CPU time 0.63 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:32 PM PDT 24
Peak memory 193052 kb
Host smart-c7562226-eacb-4ce1-9750-48e0c3169446
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007995874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2007995874
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2327512907
Short name T771
Test name
Test status
Simulation time 13232443 ps
CPU time 0.59 seconds
Started Jul 31 04:24:22 PM PDT 24
Finished Jul 31 04:24:22 PM PDT 24
Peak memory 194968 kb
Host smart-529b05e9-9e57-415d-8b60-5be2bf248a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327512907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2327512907
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2895266997
Short name T112
Test name
Test status
Simulation time 113168184 ps
CPU time 0.78 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:32 PM PDT 24
Peak memory 193980 kb
Host smart-db72aa99-c167-45af-aa61-dc52563c83d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895266997 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2895266997
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1448602692
Short name T824
Test name
Test status
Simulation time 101970279 ps
CPU time 2.06 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:34 PM PDT 24
Peak memory 196152 kb
Host smart-e48f633a-d296-4b9a-988d-3db2ce78aa0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448602692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1448602692
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.388627821
Short name T51
Test name
Test status
Simulation time 139405543 ps
CPU time 1.13 seconds
Started Jul 31 04:21:45 PM PDT 24
Finished Jul 31 04:21:46 PM PDT 24
Peak memory 198520 kb
Host smart-651e9925-b696-4ddb-992e-d528c11839d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388627821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.388627821
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1190175823
Short name T797
Test name
Test status
Simulation time 35647765 ps
CPU time 0.56 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 194196 kb
Host smart-c51b36bf-a6c1-40f5-9213-5a4cc5441a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190175823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1190175823
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.784076284
Short name T756
Test name
Test status
Simulation time 43120374 ps
CPU time 0.61 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 194940 kb
Host smart-b0df7e22-f762-4d64-8b2a-7220af325596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784076284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.784076284
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1894573373
Short name T764
Test name
Test status
Simulation time 12084383 ps
CPU time 0.64 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 194360 kb
Host smart-a86f827c-3968-4cab-a29c-4bb13cfd9177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894573373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1894573373
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.360412323
Short name T755
Test name
Test status
Simulation time 13950004 ps
CPU time 0.58 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 194300 kb
Host smart-46cf4604-c177-457a-a870-e6086d374ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360412323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.360412323
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1580102117
Short name T796
Test name
Test status
Simulation time 36069834 ps
CPU time 0.59 seconds
Started Jul 31 04:29:56 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 194348 kb
Host smart-0c48c531-1aad-4a19-b26c-2f1121c905f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580102117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1580102117
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3093971336
Short name T746
Test name
Test status
Simulation time 17192480 ps
CPU time 0.56 seconds
Started Jul 31 04:30:05 PM PDT 24
Finished Jul 31 04:30:06 PM PDT 24
Peak memory 194340 kb
Host smart-c019635d-4d06-4c3d-a580-4bbd1a84b27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093971336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3093971336
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.656269379
Short name T747
Test name
Test status
Simulation time 130790587 ps
CPU time 0.57 seconds
Started Jul 31 04:30:02 PM PDT 24
Finished Jul 31 04:30:02 PM PDT 24
Peak memory 194292 kb
Host smart-88394dce-3ade-4ff7-a2e0-f879d400cd92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656269379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.656269379
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2290654536
Short name T831
Test name
Test status
Simulation time 13724666 ps
CPU time 0.58 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 194248 kb
Host smart-f6c4bf91-79bc-4573-9eb2-c9020c0d7463
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290654536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2290654536
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1584792382
Short name T737
Test name
Test status
Simulation time 12542816 ps
CPU time 0.59 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 194336 kb
Host smart-974e475e-54a6-4ba8-9f3d-e758c9e98e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584792382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1584792382
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2729827248
Short name T752
Test name
Test status
Simulation time 45402890 ps
CPU time 0.61 seconds
Started Jul 31 04:30:04 PM PDT 24
Finished Jul 31 04:30:05 PM PDT 24
Peak memory 194320 kb
Host smart-84b7e0e4-62c1-4643-a588-2ccfc4d281b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729827248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2729827248
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1319348092
Short name T91
Test name
Test status
Simulation time 57987713 ps
CPU time 0.76 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:24:59 PM PDT 24
Peak memory 195964 kb
Host smart-320fa09c-257d-4d54-91ce-1635474154ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319348092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1319348092
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1879727142
Short name T813
Test name
Test status
Simulation time 56775591 ps
CPU time 1.99 seconds
Started Jul 31 04:23:32 PM PDT 24
Finished Jul 31 04:23:35 PM PDT 24
Peak memory 197232 kb
Host smart-9bbd8fca-82e9-43c3-a784-18564c308750
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879727142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1879727142
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2670095970
Short name T822
Test name
Test status
Simulation time 27979646 ps
CPU time 0.58 seconds
Started Jul 31 04:25:24 PM PDT 24
Finished Jul 31 04:25:25 PM PDT 24
Peak memory 194784 kb
Host smart-99fc5cc1-94e2-4c9c-86ac-002496dc161e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670095970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2670095970
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.5009308
Short name T795
Test name
Test status
Simulation time 77037441 ps
CPU time 1.03 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:23:49 PM PDT 24
Peak memory 198440 kb
Host smart-bf1967bc-b738-4df9-9187-eefe8f6593cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5009308 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.5009308
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1121585292
Short name T841
Test name
Test status
Simulation time 64071288 ps
CPU time 0.6 seconds
Started Jul 31 04:24:21 PM PDT 24
Finished Jul 31 04:24:22 PM PDT 24
Peak memory 195620 kb
Host smart-bcb869fa-d211-4e81-97b7-24196b269d08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121585292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1121585292
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.500315936
Short name T741
Test name
Test status
Simulation time 28103740 ps
CPU time 0.65 seconds
Started Jul 31 04:24:18 PM PDT 24
Finished Jul 31 04:24:18 PM PDT 24
Peak memory 195332 kb
Host smart-7cf74a55-8f7a-4b75-bc8b-74e00d0298e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500315936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.500315936
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2851409208
Short name T109
Test name
Test status
Simulation time 222368685 ps
CPU time 0.89 seconds
Started Jul 31 04:24:00 PM PDT 24
Finished Jul 31 04:24:01 PM PDT 24
Peak memory 196764 kb
Host smart-8b13fb9f-9b2d-4132-bc62-cbed56740064
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851409208 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2851409208
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.805066273
Short name T759
Test name
Test status
Simulation time 487127236 ps
CPU time 2.25 seconds
Started Jul 31 04:22:14 PM PDT 24
Finished Jul 31 04:22:17 PM PDT 24
Peak memory 198612 kb
Host smart-be0fed9e-9ccd-4df0-a486-ab923e7018ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805066273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.805066273
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3046934187
Short name T47
Test name
Test status
Simulation time 885933882 ps
CPU time 1.36 seconds
Started Jul 31 04:25:02 PM PDT 24
Finished Jul 31 04:25:04 PM PDT 24
Peak memory 198564 kb
Host smart-a9f2edad-239b-4692-a577-737a68b1a73b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046934187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3046934187
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1420206018
Short name T736
Test name
Test status
Simulation time 37227661 ps
CPU time 0.56 seconds
Started Jul 31 04:30:08 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 194884 kb
Host smart-075ebd31-f309-419a-b4c0-2d3fb20ac19f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420206018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1420206018
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.114546121
Short name T731
Test name
Test status
Simulation time 27008337 ps
CPU time 0.57 seconds
Started Jul 31 04:29:58 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 194284 kb
Host smart-31fbf3bb-c210-434f-b1b3-8437e13adaa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114546121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.114546121
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.602521308
Short name T834
Test name
Test status
Simulation time 11430195 ps
CPU time 0.61 seconds
Started Jul 31 04:30:01 PM PDT 24
Finished Jul 31 04:30:02 PM PDT 24
Peak memory 194404 kb
Host smart-fa7c4948-b734-4cba-95cf-24ac05aef3df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602521308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.602521308
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3493081795
Short name T818
Test name
Test status
Simulation time 81703611 ps
CPU time 0.59 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 194284 kb
Host smart-61470c75-9960-4f30-9cc7-8270e3ae8dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493081795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3493081795
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2940264652
Short name T788
Test name
Test status
Simulation time 148401866 ps
CPU time 0.58 seconds
Started Jul 31 04:30:01 PM PDT 24
Finished Jul 31 04:30:01 PM PDT 24
Peak memory 194412 kb
Host smart-d0ba920a-a8f4-4d62-816e-f0578552800e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940264652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2940264652
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.633464405
Short name T835
Test name
Test status
Simulation time 249262834 ps
CPU time 0.6 seconds
Started Jul 31 04:30:40 PM PDT 24
Finished Jul 31 04:30:40 PM PDT 24
Peak memory 194340 kb
Host smart-48064892-ea54-4ebf-8faa-0cc6a12afc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633464405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.633464405
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.389059955
Short name T807
Test name
Test status
Simulation time 31741873 ps
CPU time 0.55 seconds
Started Jul 31 04:30:39 PM PDT 24
Finished Jul 31 04:30:40 PM PDT 24
Peak memory 194936 kb
Host smart-441019d0-6b10-4314-84a2-cc3e193ee780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389059955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.389059955
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.96544058
Short name T730
Test name
Test status
Simulation time 16710077 ps
CPU time 0.59 seconds
Started Jul 31 04:30:01 PM PDT 24
Finished Jul 31 04:30:02 PM PDT 24
Peak memory 194344 kb
Host smart-9769664d-2468-4482-bdb2-631797c6d298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96544058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.96544058
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2047724139
Short name T754
Test name
Test status
Simulation time 16225219 ps
CPU time 0.58 seconds
Started Jul 31 04:30:03 PM PDT 24
Finished Jul 31 04:30:03 PM PDT 24
Peak memory 194272 kb
Host smart-a80ab402-1368-486e-9432-e2711ba458a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047724139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2047724139
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3294329883
Short name T762
Test name
Test status
Simulation time 54449603 ps
CPU time 0.58 seconds
Started Jul 31 04:30:00 PM PDT 24
Finished Jul 31 04:30:01 PM PDT 24
Peak memory 194376 kb
Host smart-bbf8afbf-3379-4478-a67f-334ac2f5565f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294329883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3294329883
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3135585968
Short name T786
Test name
Test status
Simulation time 222323566 ps
CPU time 0.72 seconds
Started Jul 31 04:25:23 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 196700 kb
Host smart-6028f952-43e3-4156-83d1-5d561f123fc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135585968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3135585968
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.160096095
Short name T87
Test name
Test status
Simulation time 1061442058 ps
CPU time 1.42 seconds
Started Jul 31 04:24:53 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 197240 kb
Host smart-68108017-66eb-436d-8de9-f50bc6de8b7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160096095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.160096095
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2743949084
Short name T837
Test name
Test status
Simulation time 12784952 ps
CPU time 0.58 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 195064 kb
Host smart-bd9afbc9-fb38-4684-9f14-913902e79b58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743949084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2743949084
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1608525928
Short name T748
Test name
Test status
Simulation time 85680209 ps
CPU time 1.11 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 198456 kb
Host smart-9f1b63a0-6fdd-4d53-b300-d051e2efb208
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608525928 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1608525928
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3667577329
Short name T829
Test name
Test status
Simulation time 35387800 ps
CPU time 0.6 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 195368 kb
Host smart-14ba494a-081e-4b50-8a15-cac6a156f17c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667577329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3667577329
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1819147750
Short name T802
Test name
Test status
Simulation time 12559847 ps
CPU time 0.59 seconds
Started Jul 31 04:25:23 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 194136 kb
Host smart-a6fbb741-9ddf-4966-8fac-abe4c970d183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819147750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1819147750
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3279761853
Short name T787
Test name
Test status
Simulation time 55382876 ps
CPU time 0.64 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 195748 kb
Host smart-305018c6-4bee-4705-9dbd-78a50a589bbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279761853 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3279761853
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.326842983
Short name T724
Test name
Test status
Simulation time 358802050 ps
CPU time 1.84 seconds
Started Jul 31 04:21:56 PM PDT 24
Finished Jul 31 04:21:58 PM PDT 24
Peak memory 198624 kb
Host smart-a4536eb2-cd9b-4427-98f7-b006b1c283e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326842983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.326842983
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3527062998
Short name T789
Test name
Test status
Simulation time 455602347 ps
CPU time 1.44 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:20:54 PM PDT 24
Peak memory 198576 kb
Host smart-63ea98e1-0d62-48bb-95aa-b07e1aa60f1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527062998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3527062998
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.495226638
Short name T793
Test name
Test status
Simulation time 12007022 ps
CPU time 0.56 seconds
Started Jul 31 04:30:10 PM PDT 24
Finished Jul 31 04:30:11 PM PDT 24
Peak memory 194252 kb
Host smart-13b333d2-209a-4970-b61b-ca0a8cde83f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495226638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.495226638
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.62608222
Short name T735
Test name
Test status
Simulation time 69755206 ps
CPU time 0.57 seconds
Started Jul 31 04:30:00 PM PDT 24
Finished Jul 31 04:30:01 PM PDT 24
Peak memory 194292 kb
Host smart-e7aa802a-1eb5-4ac5-9b37-bc77e9405089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62608222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.62608222
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.696098643
Short name T774
Test name
Test status
Simulation time 51870495 ps
CPU time 0.59 seconds
Started Jul 31 04:30:30 PM PDT 24
Finished Jul 31 04:30:31 PM PDT 24
Peak memory 194912 kb
Host smart-e77c4f74-4182-490d-a6d2-6f4a28d5a9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696098643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.696098643
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3436923119
Short name T830
Test name
Test status
Simulation time 18798549 ps
CPU time 0.62 seconds
Started Jul 31 04:30:06 PM PDT 24
Finished Jul 31 04:30:07 PM PDT 24
Peak memory 194368 kb
Host smart-3445b6aa-5623-4efa-af09-059f71f2db3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436923119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3436923119
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2048146218
Short name T721
Test name
Test status
Simulation time 24698900 ps
CPU time 0.57 seconds
Started Jul 31 04:30:37 PM PDT 24
Finished Jul 31 04:30:38 PM PDT 24
Peak memory 194936 kb
Host smart-5ab432cb-66cb-4c67-a998-c2041d142717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048146218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2048146218
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2867901362
Short name T738
Test name
Test status
Simulation time 16512155 ps
CPU time 0.58 seconds
Started Jul 31 04:30:11 PM PDT 24
Finished Jul 31 04:30:11 PM PDT 24
Peak memory 194420 kb
Host smart-2f8e0eb4-114c-4369-a792-067471690a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867901362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2867901362
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1635238969
Short name T742
Test name
Test status
Simulation time 11296282 ps
CPU time 0.58 seconds
Started Jul 31 04:30:04 PM PDT 24
Finished Jul 31 04:30:05 PM PDT 24
Peak memory 194948 kb
Host smart-fa046005-6689-4c14-9581-6b34fc20f36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635238969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1635238969
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.603736127
Short name T820
Test name
Test status
Simulation time 30168609 ps
CPU time 0.58 seconds
Started Jul 31 04:30:12 PM PDT 24
Finished Jul 31 04:30:13 PM PDT 24
Peak memory 194916 kb
Host smart-9938c153-de45-4d24-9a29-d11cc1431f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603736127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.603736127
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.165708068
Short name T821
Test name
Test status
Simulation time 16506673 ps
CPU time 0.56 seconds
Started Jul 31 04:30:01 PM PDT 24
Finished Jul 31 04:30:01 PM PDT 24
Peak memory 194264 kb
Host smart-6aca9cbc-69d2-456a-a9d3-ae176c700cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165708068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.165708068
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1201307392
Short name T780
Test name
Test status
Simulation time 11438120 ps
CPU time 0.61 seconds
Started Jul 31 04:30:00 PM PDT 24
Finished Jul 31 04:30:01 PM PDT 24
Peak memory 194288 kb
Host smart-15756a3f-d9e3-4e08-94a4-c7cb367af5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201307392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1201307392
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3947756422
Short name T725
Test name
Test status
Simulation time 34009851 ps
CPU time 0.92 seconds
Started Jul 31 04:24:39 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 197124 kb
Host smart-289f42e3-544e-4230-8443-190ead2cd9d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947756422 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3947756422
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2438661194
Short name T98
Test name
Test status
Simulation time 25233056 ps
CPU time 0.58 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 194980 kb
Host smart-93f31b58-aace-4ef0-8401-ee30c04cb472
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438661194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2438661194
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.645320855
Short name T809
Test name
Test status
Simulation time 14640912 ps
CPU time 0.62 seconds
Started Jul 31 04:21:48 PM PDT 24
Finished Jul 31 04:21:49 PM PDT 24
Peak memory 194376 kb
Host smart-b6944b69-eb4f-45b5-b6d2-96e890af7c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645320855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.645320855
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3228330187
Short name T107
Test name
Test status
Simulation time 28959065 ps
CPU time 0.86 seconds
Started Jul 31 04:22:44 PM PDT 24
Finished Jul 31 04:22:45 PM PDT 24
Peak memory 197400 kb
Host smart-dc66f54f-2afe-4fdb-a4f5-600cf3ed9f2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228330187 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3228330187
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.731223463
Short name T723
Test name
Test status
Simulation time 375350360 ps
CPU time 2.31 seconds
Started Jul 31 04:23:32 PM PDT 24
Finished Jul 31 04:23:35 PM PDT 24
Peak memory 197352 kb
Host smart-d5848a6e-5022-4435-a545-9956963bad75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731223463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.731223463
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.459810560
Short name T48
Test name
Test status
Simulation time 148169314 ps
CPU time 0.8 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:20:53 PM PDT 24
Peak memory 198072 kb
Host smart-b5752376-3c63-47a5-92f7-40d0d4869c22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459810560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.459810560
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1054811031
Short name T733
Test name
Test status
Simulation time 34432484 ps
CPU time 0.88 seconds
Started Jul 31 04:29:16 PM PDT 24
Finished Jul 31 04:29:17 PM PDT 24
Peak memory 198476 kb
Host smart-5850d2a7-ffa9-4b21-a590-09cc405c5152
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054811031 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1054811031
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2173873836
Short name T772
Test name
Test status
Simulation time 22311748 ps
CPU time 0.59 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 193584 kb
Host smart-7d0466ce-96a1-4bf0-a5c6-c79b366e9123
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173873836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2173873836
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3371784846
Short name T775
Test name
Test status
Simulation time 228914887 ps
CPU time 0.58 seconds
Started Jul 31 04:29:21 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 194332 kb
Host smart-324b5e57-5913-41ec-a7cf-e0dfec3825e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371784846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3371784846
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1534756499
Short name T106
Test name
Test status
Simulation time 97733492 ps
CPU time 0.7 seconds
Started Jul 31 04:29:12 PM PDT 24
Finished Jul 31 04:29:12 PM PDT 24
Peak memory 196392 kb
Host smart-201648e6-afd4-40e4-b155-6a3efbb9ed20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534756499 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1534756499
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1046335657
Short name T768
Test name
Test status
Simulation time 1808867202 ps
CPU time 2.25 seconds
Started Jul 31 04:29:11 PM PDT 24
Finished Jul 31 04:29:14 PM PDT 24
Peak memory 198688 kb
Host smart-20d823c2-25f4-4c13-8f0e-e438ad161795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046335657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1046335657
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4237222371
Short name T803
Test name
Test status
Simulation time 134630791 ps
CPU time 0.83 seconds
Started Jul 31 04:29:17 PM PDT 24
Finished Jul 31 04:29:18 PM PDT 24
Peak memory 197464 kb
Host smart-b4018470-0cd7-4137-8321-19b7e7e7f828
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237222371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.4237222371
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1955741815
Short name T826
Test name
Test status
Simulation time 177725862 ps
CPU time 1.55 seconds
Started Jul 31 04:29:20 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 198652 kb
Host smart-59fd2086-2a5a-407e-9c56-01fb3f21dcce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955741815 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1955741815
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3527275118
Short name T94
Test name
Test status
Simulation time 12510298 ps
CPU time 0.6 seconds
Started Jul 31 04:29:47 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 195492 kb
Host smart-1801e21e-9fa9-4f4b-8b1e-12dbe0f1f7a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527275118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3527275118
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2812123242
Short name T732
Test name
Test status
Simulation time 12447380 ps
CPU time 0.54 seconds
Started Jul 31 04:29:21 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 194896 kb
Host smart-ba4a92b3-484d-490f-9283-2b77e72107b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812123242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2812123242
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3175915456
Short name T105
Test name
Test status
Simulation time 43079488 ps
CPU time 0.65 seconds
Started Jul 31 04:29:29 PM PDT 24
Finished Jul 31 04:29:29 PM PDT 24
Peak memory 195452 kb
Host smart-6496182f-bcc7-4a8b-859d-1c5ea56c7fd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175915456 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3175915456
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3968666309
Short name T784
Test name
Test status
Simulation time 145944704 ps
CPU time 2.74 seconds
Started Jul 31 04:29:20 PM PDT 24
Finished Jul 31 04:29:23 PM PDT 24
Peak memory 198588 kb
Host smart-c0820ea6-e0a0-4d8e-9302-50e2e64561ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968666309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3968666309
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3081303396
Short name T769
Test name
Test status
Simulation time 26622755 ps
CPU time 0.81 seconds
Started Jul 31 04:29:22 PM PDT 24
Finished Jul 31 04:29:23 PM PDT 24
Peak memory 198480 kb
Host smart-0721cd1e-63a4-4306-a642-5dfbfb5d47e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081303396 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3081303396
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3854836955
Short name T100
Test name
Test status
Simulation time 56354272 ps
CPU time 0.6 seconds
Started Jul 31 04:29:20 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 195376 kb
Host smart-c80db8c1-7b7e-4817-a7e9-0d9606e69614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854836955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3854836955
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1625727703
Short name T781
Test name
Test status
Simulation time 13632367 ps
CPU time 0.61 seconds
Started Jul 31 04:29:20 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 194356 kb
Host smart-f4936d7c-af22-45da-b74b-1960ec0cf44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625727703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1625727703
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3728342100
Short name T90
Test name
Test status
Simulation time 46161381 ps
CPU time 0.56 seconds
Started Jul 31 04:29:19 PM PDT 24
Finished Jul 31 04:29:20 PM PDT 24
Peak memory 194788 kb
Host smart-a18c5f63-6e61-41ef-a322-7ba2d76259f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728342100 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3728342100
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.228977789
Short name T810
Test name
Test status
Simulation time 238001065 ps
CPU time 1.48 seconds
Started Jul 31 04:29:20 PM PDT 24
Finished Jul 31 04:29:22 PM PDT 24
Peak memory 198596 kb
Host smart-7e85307f-a06d-43a0-90bb-e347d31c2362
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228977789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.228977789
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3581849005
Short name T758
Test name
Test status
Simulation time 620128617 ps
CPU time 0.85 seconds
Started Jul 31 04:29:19 PM PDT 24
Finished Jul 31 04:29:20 PM PDT 24
Peak memory 198340 kb
Host smart-4543b5cc-68c6-4c4b-8fa5-69ae01b85b7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581849005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3581849005
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3424945890
Short name T840
Test name
Test status
Simulation time 25986991 ps
CPU time 0.79 seconds
Started Jul 31 04:29:47 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 198488 kb
Host smart-0d6b3088-a833-426f-9c15-8b69937f5437
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424945890 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3424945890
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3709042853
Short name T734
Test name
Test status
Simulation time 14001351 ps
CPU time 0.63 seconds
Started Jul 31 04:29:19 PM PDT 24
Finished Jul 31 04:29:20 PM PDT 24
Peak memory 195128 kb
Host smart-6bd58469-3f58-4d0b-9e30-925c84d0eab4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709042853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3709042853
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1995967220
Short name T765
Test name
Test status
Simulation time 42680884 ps
CPU time 0.55 seconds
Started Jul 31 04:29:20 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 194896 kb
Host smart-b23f048b-ed24-4708-8a3d-01d9b24c1c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995967220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1995967220
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2182884410
Short name T833
Test name
Test status
Simulation time 63370316 ps
CPU time 0.78 seconds
Started Jul 31 04:29:21 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 197608 kb
Host smart-17da631a-5a7a-4909-8bc9-c5a1237355a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182884410 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2182884410
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2286944626
Short name T761
Test name
Test status
Simulation time 425845780 ps
CPU time 2.55 seconds
Started Jul 31 04:29:24 PM PDT 24
Finished Jul 31 04:29:26 PM PDT 24
Peak memory 198580 kb
Host smart-e952ac52-a6a1-408a-a184-75f4d4ca9df6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286944626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2286944626
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2132576849
Short name T35
Test name
Test status
Simulation time 1405300038 ps
CPU time 1.41 seconds
Started Jul 31 04:29:19 PM PDT 24
Finished Jul 31 04:29:21 PM PDT 24
Peak memory 198508 kb
Host smart-d52989c4-85d2-48bf-aa00-23adc5bff08f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132576849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2132576849
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1330593118
Short name T222
Test name
Test status
Simulation time 32035728 ps
CPU time 0.55 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 193320 kb
Host smart-978d9af6-2c32-423f-8352-a8cbad9a7ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330593118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1330593118
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3113884847
Short name T685
Test name
Test status
Simulation time 132687728 ps
CPU time 0.66 seconds
Started Jul 31 04:24:46 PM PDT 24
Finished Jul 31 04:24:47 PM PDT 24
Peak memory 193116 kb
Host smart-9dfd1732-1682-41d7-85d2-043affffa959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113884847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3113884847
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.739062238
Short name T467
Test name
Test status
Simulation time 889541002 ps
CPU time 21.71 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:26:10 PM PDT 24
Peak memory 197120 kb
Host smart-9fe5af42-fba6-42a1-92ba-a6c22bf3b21e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739062238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.739062238
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.248426246
Short name T10
Test name
Test status
Simulation time 304091568 ps
CPU time 0.94 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 197408 kb
Host smart-d78a0aaf-861b-4531-97f2-7e7b91c8be71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248426246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.248426246
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3093901108
Short name T365
Test name
Test status
Simulation time 147163016 ps
CPU time 0.83 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:25:33 PM PDT 24
Peak memory 195128 kb
Host smart-79b7e91b-05aa-432f-9618-61a612868263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093901108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3093901108
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.506104416
Short name T231
Test name
Test status
Simulation time 44719959 ps
CPU time 1.72 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 196996 kb
Host smart-89cf914b-1e8b-4ca9-8e5b-b88b58b84669
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506104416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.506104416
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1823191653
Short name T586
Test name
Test status
Simulation time 207944304 ps
CPU time 1.97 seconds
Started Jul 31 04:20:55 PM PDT 24
Finished Jul 31 04:20:57 PM PDT 24
Peak memory 196588 kb
Host smart-c2ad0ce5-268d-409f-99b0-1cef5d7d3aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823191653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1823191653
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.386846138
Short name T282
Test name
Test status
Simulation time 25792844 ps
CPU time 0.92 seconds
Started Jul 31 04:22:26 PM PDT 24
Finished Jul 31 04:22:27 PM PDT 24
Peak memory 196304 kb
Host smart-ac02d85f-572c-4d77-871c-e3d33d1f5651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386846138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.386846138
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1463866780
Short name T610
Test name
Test status
Simulation time 32980199 ps
CPU time 0.83 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 197024 kb
Host smart-59d3aba2-4fc4-460f-9f90-a0ae9105e8fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463866780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1463866780
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4114127481
Short name T451
Test name
Test status
Simulation time 285162176 ps
CPU time 3.16 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:12 PM PDT 24
Peak memory 197180 kb
Host smart-322c19cc-4165-4df1-98a0-a1a498868a0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114127481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4114127481
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1089733
Short name T54
Test name
Test status
Simulation time 182290963 ps
CPU time 0.76 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 213816 kb
Host smart-d98b7a16-9767-42de-b97e-c1a7924aa009
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1089733
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1300631351
Short name T17
Test name
Test status
Simulation time 142363304 ps
CPU time 1.18 seconds
Started Jul 31 04:20:36 PM PDT 24
Finished Jul 31 04:20:37 PM PDT 24
Peak memory 195908 kb
Host smart-54ee9170-f1a3-404e-b2e9-b2780e62c168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300631351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1300631351
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1739338480
Short name T449
Test name
Test status
Simulation time 193651874 ps
CPU time 1.28 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:20:53 PM PDT 24
Peak memory 196868 kb
Host smart-3c9c7ab2-5418-470c-a864-7d5a94801e50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739338480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1739338480
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3459532445
Short name T305
Test name
Test status
Simulation time 6993372663 ps
CPU time 72.18 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:25:52 PM PDT 24
Peak memory 197400 kb
Host smart-ec255f9a-637a-4725-a36a-0817030829a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459532445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3459532445
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2627004027
Short name T32
Test name
Test status
Simulation time 81084272577 ps
CPU time 1808.73 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:55:57 PM PDT 24
Peak memory 198704 kb
Host smart-19c08995-856e-4c47-bc93-a62fc82c6458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2627004027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2627004027
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2197430439
Short name T276
Test name
Test status
Simulation time 21768139 ps
CPU time 0.56 seconds
Started Jul 31 04:36:25 PM PDT 24
Finished Jul 31 04:36:26 PM PDT 24
Peak memory 194972 kb
Host smart-0fe68022-6f0f-425c-8338-4852205441a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197430439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2197430439
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1095361080
Short name T189
Test name
Test status
Simulation time 67751572 ps
CPU time 0.66 seconds
Started Jul 31 04:24:39 PM PDT 24
Finished Jul 31 04:24:39 PM PDT 24
Peak memory 193988 kb
Host smart-74f6bda5-6c56-4b4c-b4db-f13e0840f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095361080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1095361080
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.938588117
Short name T526
Test name
Test status
Simulation time 594544396 ps
CPU time 17.23 seconds
Started Jul 31 04:36:27 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 196688 kb
Host smart-5ee34ab0-4fb1-49c7-ae4d-b812f4db273e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938588117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.938588117
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2568740410
Short name T63
Test name
Test status
Simulation time 227551466 ps
CPU time 0.83 seconds
Started Jul 31 04:36:25 PM PDT 24
Finished Jul 31 04:36:25 PM PDT 24
Peak memory 196472 kb
Host smart-9147b144-359b-4df5-a17a-6a411645b69a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568740410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2568740410
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2638355286
Short name T236
Test name
Test status
Simulation time 243577022 ps
CPU time 1.03 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 197336 kb
Host smart-7df93f05-2579-4f29-9405-6963501b24bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638355286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2638355286
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.123375073
Short name T226
Test name
Test status
Simulation time 129267861 ps
CPU time 1.94 seconds
Started Jul 31 04:36:24 PM PDT 24
Finished Jul 31 04:36:26 PM PDT 24
Peak memory 198344 kb
Host smart-7037128b-12eb-4cc2-8803-c79222251916
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123375073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.123375073
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1525551192
Short name T330
Test name
Test status
Simulation time 149107946 ps
CPU time 1.54 seconds
Started Jul 31 04:36:22 PM PDT 24
Finished Jul 31 04:36:24 PM PDT 24
Peak memory 196540 kb
Host smart-795713b7-4723-443d-96bc-2601155741d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525551192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1525551192
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2260956822
Short name T703
Test name
Test status
Simulation time 112449806 ps
CPU time 0.86 seconds
Started Jul 31 04:25:06 PM PDT 24
Finished Jul 31 04:25:07 PM PDT 24
Peak memory 196228 kb
Host smart-5f85e5f4-7a51-4186-bedb-76b29bfcaf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260956822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2260956822
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.150992875
Short name T700
Test name
Test status
Simulation time 113272339 ps
CPU time 1.03 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 196196 kb
Host smart-e28bf993-c1a0-48b2-8531-db71e57ed766
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150992875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.150992875
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1441370546
Short name T444
Test name
Test status
Simulation time 421275514 ps
CPU time 4.65 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:28 PM PDT 24
Peak memory 198340 kb
Host smart-553ec794-fd53-4bab-b82a-9f36bfdc6b82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441370546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1441370546
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2812820121
Short name T38
Test name
Test status
Simulation time 107796426 ps
CPU time 0.97 seconds
Started Jul 31 04:36:25 PM PDT 24
Finished Jul 31 04:36:26 PM PDT 24
Peak memory 215324 kb
Host smart-9da6b13c-2fef-4b4a-a770-f738909a4fd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812820121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2812820121
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3180530975
Short name T399
Test name
Test status
Simulation time 69374861 ps
CPU time 0.71 seconds
Started Jul 31 04:22:49 PM PDT 24
Finished Jul 31 04:22:50 PM PDT 24
Peak memory 194476 kb
Host smart-bf3bf4bc-b27c-450a-bf47-90f6a8e13120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180530975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3180530975
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1419339637
Short name T411
Test name
Test status
Simulation time 441172493 ps
CPU time 1.25 seconds
Started Jul 31 04:22:06 PM PDT 24
Finished Jul 31 04:22:07 PM PDT 24
Peak memory 197060 kb
Host smart-ffffdf7d-5b3e-4e44-9292-5a34d6f51261
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419339637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1419339637
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.174963883
Short name T503
Test name
Test status
Simulation time 13427173577 ps
CPU time 159.38 seconds
Started Jul 31 04:36:26 PM PDT 24
Finished Jul 31 04:39:05 PM PDT 24
Peak memory 198516 kb
Host smart-1676b952-90f2-4bbd-a7bb-457c9ff11b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174963883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.174963883
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1263864602
Short name T67
Test name
Test status
Simulation time 96737330564 ps
CPU time 1894.3 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 05:07:58 PM PDT 24
Peak memory 198716 kb
Host smart-ef92487c-b773-45e2-a77e-b4428b3afdb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1263864602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1263864602
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.4250604501
Short name T478
Test name
Test status
Simulation time 81128128 ps
CPU time 0.94 seconds
Started Jul 31 04:36:53 PM PDT 24
Finished Jul 31 04:36:54 PM PDT 24
Peak memory 197052 kb
Host smart-b432879c-101d-46bc-9edf-1fded10ced55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250604501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.4250604501
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.851193054
Short name T396
Test name
Test status
Simulation time 791776363 ps
CPU time 22.8 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 197204 kb
Host smart-ae5c23d6-e352-485d-87ee-978651f0cbe4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851193054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.851193054
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3335940038
Short name T281
Test name
Test status
Simulation time 31867189 ps
CPU time 0.71 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:36:48 PM PDT 24
Peak memory 195672 kb
Host smart-ba273d05-e8e8-4c68-83f9-a819b5fb2244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335940038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3335940038
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1681911702
Short name T688
Test name
Test status
Simulation time 85248823 ps
CPU time 0.81 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 195964 kb
Host smart-50066a44-7917-48e1-95ea-cb4995fde59c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681911702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1681911702
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.4290319734
Short name T291
Test name
Test status
Simulation time 41251603 ps
CPU time 1.84 seconds
Started Jul 31 04:36:53 PM PDT 24
Finished Jul 31 04:36:55 PM PDT 24
Peak memory 198544 kb
Host smart-9b12381c-54a3-4ee5-b943-d5737a69d60d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290319734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.4290319734
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3964988801
Short name T207
Test name
Test status
Simulation time 136489927 ps
CPU time 1.73 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 196292 kb
Host smart-3b57b02d-d425-4206-bca1-8665859d7557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964988801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3964988801
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2137840408
Short name T338
Test name
Test status
Simulation time 104126437 ps
CPU time 0.88 seconds
Started Jul 31 04:36:51 PM PDT 24
Finished Jul 31 04:36:52 PM PDT 24
Peak memory 196452 kb
Host smart-5a03df10-9387-4c92-9982-a904c20f8356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137840408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2137840408
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1024013584
Short name T216
Test name
Test status
Simulation time 20222850 ps
CPU time 0.84 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:36:48 PM PDT 24
Peak memory 197528 kb
Host smart-51e78145-d9ff-4a73-9423-a6f20e4d1a7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024013584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1024013584
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3466809146
Short name T522
Test name
Test status
Simulation time 290557666 ps
CPU time 4.87 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:36:52 PM PDT 24
Peak memory 198436 kb
Host smart-20005ac0-29d2-4e34-b92b-271b17afeecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466809146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3466809146
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.869574262
Short name T119
Test name
Test status
Simulation time 102950043 ps
CPU time 0.76 seconds
Started Jul 31 04:36:50 PM PDT 24
Finished Jul 31 04:36:51 PM PDT 24
Peak memory 196416 kb
Host smart-63ad7244-8bcd-427b-ba2a-f7703ce6ba32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869574262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.869574262
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4208717975
Short name T209
Test name
Test status
Simulation time 167185996 ps
CPU time 0.9 seconds
Started Jul 31 04:36:46 PM PDT 24
Finished Jul 31 04:36:47 PM PDT 24
Peak memory 196804 kb
Host smart-9fc98699-8eda-4c2d-a10a-480781846d5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208717975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4208717975
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2218994299
Short name T44
Test name
Test status
Simulation time 9347598709 ps
CPU time 58.02 seconds
Started Jul 31 04:36:49 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 198612 kb
Host smart-a663805c-ae8f-4166-a6d9-e2a32f5dffdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218994299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2218994299
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3677870294
Short name T332
Test name
Test status
Simulation time 46279953 ps
CPU time 0.57 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:00 PM PDT 24
Peak memory 194308 kb
Host smart-17a672d2-d79b-44cd-bfd1-3c275480b2df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677870294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3677870294
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1394932397
Short name T140
Test name
Test status
Simulation time 18805659 ps
CPU time 0.66 seconds
Started Jul 31 04:36:54 PM PDT 24
Finished Jul 31 04:36:55 PM PDT 24
Peak memory 194472 kb
Host smart-0757e6c4-90c1-404a-b22a-cef269eabcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394932397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1394932397
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1143969751
Short name T417
Test name
Test status
Simulation time 2147612770 ps
CPU time 27.33 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 196128 kb
Host smart-76059514-3ab2-4c1d-b0de-8278ab0f5fb0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143969751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1143969751
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3288481518
Short name T561
Test name
Test status
Simulation time 139913227 ps
CPU time 0.82 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:36:56 PM PDT 24
Peak memory 196308 kb
Host smart-b1241e4f-50df-4231-bfab-589162ebd844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288481518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3288481518
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2655851597
Short name T317
Test name
Test status
Simulation time 207094324 ps
CPU time 0.91 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:36:56 PM PDT 24
Peak memory 197816 kb
Host smart-9610f5fe-7ea1-4c53-b2df-6a92358a239d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655851597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2655851597
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.4139575936
Short name T534
Test name
Test status
Simulation time 129397893 ps
CPU time 2.47 seconds
Started Jul 31 04:36:57 PM PDT 24
Finished Jul 31 04:37:00 PM PDT 24
Peak memory 198552 kb
Host smart-8991bd48-af70-42e5-8580-ac3543aa94af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139575936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.4139575936
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.14105733
Short name T595
Test name
Test status
Simulation time 662139977 ps
CPU time 3.15 seconds
Started Jul 31 04:36:57 PM PDT 24
Finished Jul 31 04:37:00 PM PDT 24
Peak memory 196952 kb
Host smart-b24d2730-283e-4f05-a6b1-2c8e39557b5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14105733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.14105733
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1692598074
Short name T350
Test name
Test status
Simulation time 33053797 ps
CPU time 1.1 seconds
Started Jul 31 04:36:49 PM PDT 24
Finished Jul 31 04:36:50 PM PDT 24
Peak memory 196512 kb
Host smart-66aeefee-c0bc-48f6-8ca5-275eaaed60be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692598074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1692598074
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.834643748
Short name T117
Test name
Test status
Simulation time 26466760 ps
CPU time 0.75 seconds
Started Jul 31 04:36:50 PM PDT 24
Finished Jul 31 04:36:51 PM PDT 24
Peak memory 195768 kb
Host smart-0e44153f-af23-488b-98d6-fdd84cc1355a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834643748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.834643748
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3657264312
Short name T559
Test name
Test status
Simulation time 271228105 ps
CPU time 5.47 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:37:00 PM PDT 24
Peak memory 198336 kb
Host smart-f0d3681e-9b98-40c4-bd4a-2bc7cc1d2784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657264312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3657264312
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.855529165
Short name T353
Test name
Test status
Simulation time 40185059 ps
CPU time 0.8 seconds
Started Jul 31 04:36:50 PM PDT 24
Finished Jul 31 04:36:51 PM PDT 24
Peak memory 196472 kb
Host smart-45923273-ee3e-4cd5-b94a-d864592ee1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855529165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.855529165
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3718192278
Short name T582
Test name
Test status
Simulation time 69136083 ps
CPU time 1.28 seconds
Started Jul 31 04:36:50 PM PDT 24
Finished Jul 31 04:36:51 PM PDT 24
Peak memory 195932 kb
Host smart-f80245f1-c10e-4055-9006-01830a159d4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718192278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3718192278
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1245905790
Short name T300
Test name
Test status
Simulation time 2113431319 ps
CPU time 25.57 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 198428 kb
Host smart-de0b1aa5-a5a1-4421-8d40-e2471091aee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245905790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1245905790
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3472758648
Short name T623
Test name
Test status
Simulation time 40689263 ps
CPU time 0.59 seconds
Started Jul 31 04:37:05 PM PDT 24
Finished Jul 31 04:37:06 PM PDT 24
Peak memory 194504 kb
Host smart-67190517-2b34-453c-8c53-52e8d323d472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472758648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3472758648
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.588480791
Short name T333
Test name
Test status
Simulation time 52485061 ps
CPU time 0.66 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:36:56 PM PDT 24
Peak memory 194540 kb
Host smart-9bca7720-d419-4f1f-9789-df0108d86f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588480791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.588480791
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.262143575
Short name T673
Test name
Test status
Simulation time 504996379 ps
CPU time 8.33 seconds
Started Jul 31 04:36:54 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 197344 kb
Host smart-2d893a0a-2c77-46d7-a761-e15710edb286
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262143575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.262143575
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.570202125
Short name T204
Test name
Test status
Simulation time 78393967 ps
CPU time 1.11 seconds
Started Jul 31 04:36:56 PM PDT 24
Finished Jul 31 04:36:57 PM PDT 24
Peak memory 197108 kb
Host smart-2b2d8822-59c3-4feb-b04b-84f6bec24585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570202125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.570202125
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.815217201
Short name T419
Test name
Test status
Simulation time 44883245 ps
CPU time 0.85 seconds
Started Jul 31 04:36:57 PM PDT 24
Finished Jul 31 04:36:58 PM PDT 24
Peak memory 195912 kb
Host smart-cd546a5e-ad31-4956-86ba-baf3c5d3fb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815217201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.815217201
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2034033457
Short name T424
Test name
Test status
Simulation time 118469644 ps
CPU time 1.25 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:36:57 PM PDT 24
Peak memory 196868 kb
Host smart-7929b4c1-eb95-4a5e-a5cd-8d86a77c6b28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034033457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2034033457
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1916733116
Short name T470
Test name
Test status
Simulation time 85004039 ps
CPU time 1.76 seconds
Started Jul 31 04:36:57 PM PDT 24
Finished Jul 31 04:36:59 PM PDT 24
Peak memory 196268 kb
Host smart-5415d668-d4b1-4093-9c76-86d9ad39604c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916733116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1916733116
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.528545862
Short name T398
Test name
Test status
Simulation time 24351700 ps
CPU time 0.8 seconds
Started Jul 31 04:36:55 PM PDT 24
Finished Jul 31 04:36:56 PM PDT 24
Peak memory 196868 kb
Host smart-933b88bb-df88-4aae-9f89-f98bf9b9a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528545862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.528545862
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1684497524
Short name T275
Test name
Test status
Simulation time 142589369 ps
CPU time 0.72 seconds
Started Jul 31 04:36:54 PM PDT 24
Finished Jul 31 04:36:55 PM PDT 24
Peak memory 195740 kb
Host smart-bb130c52-6fee-47a9-8ec6-68b75eee0880
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684497524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1684497524
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3720303222
Short name T517
Test name
Test status
Simulation time 204251846 ps
CPU time 3.53 seconds
Started Jul 31 04:36:56 PM PDT 24
Finished Jul 31 04:36:59 PM PDT 24
Peak memory 198420 kb
Host smart-1dba1ed8-c837-4430-8d88-e1e79d80c9f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720303222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3720303222
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2502348348
Short name T355
Test name
Test status
Simulation time 731864763 ps
CPU time 1.21 seconds
Started Jul 31 04:36:57 PM PDT 24
Finished Jul 31 04:36:58 PM PDT 24
Peak memory 196684 kb
Host smart-072cd2ff-9ba8-4ca8-a72a-e67e2720e771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502348348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2502348348
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.670026645
Short name T708
Test name
Test status
Simulation time 107328329 ps
CPU time 0.9 seconds
Started Jul 31 04:37:01 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 196884 kb
Host smart-42ec43b0-ed61-4710-8ea2-52b6a8f3df99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670026645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.670026645
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3870764996
Short name T452
Test name
Test status
Simulation time 10878152091 ps
CPU time 144.83 seconds
Started Jul 31 04:36:57 PM PDT 24
Finished Jul 31 04:39:22 PM PDT 24
Peak memory 192164 kb
Host smart-96f53906-da3d-4bf1-8fea-77137928dfc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870764996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3870764996
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2664211164
Short name T670
Test name
Test status
Simulation time 35658628778 ps
CPU time 282.32 seconds
Started Jul 31 04:36:56 PM PDT 24
Finished Jul 31 04:41:38 PM PDT 24
Peak memory 198756 kb
Host smart-08cc61b9-c2e2-4795-95f2-4d137007ea0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2664211164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2664211164
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.11018274
Short name T621
Test name
Test status
Simulation time 11197372 ps
CPU time 0.56 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:03 PM PDT 24
Peak memory 194284 kb
Host smart-69d89e74-4239-4c08-be21-a17390de0ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11018274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.11018274
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.818124570
Short name T239
Test name
Test status
Simulation time 82895034 ps
CPU time 0.81 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 195856 kb
Host smart-f041eb60-9dc8-4b82-af3e-b63dc3d1cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818124570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.818124570
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2126612106
Short name T597
Test name
Test status
Simulation time 4382704088 ps
CPU time 24.44 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:24 PM PDT 24
Peak memory 197260 kb
Host smart-0881544a-359f-42d1-9574-d402a355cf2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126612106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2126612106
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3614714415
Short name T242
Test name
Test status
Simulation time 323889643 ps
CPU time 1.11 seconds
Started Jul 31 04:37:05 PM PDT 24
Finished Jul 31 04:37:06 PM PDT 24
Peak memory 196816 kb
Host smart-04edaf31-e5a5-47c2-8730-af815d2324c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614714415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3614714415
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2670996574
Short name T547
Test name
Test status
Simulation time 63529224 ps
CPU time 0.98 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 196468 kb
Host smart-b404dcef-d48e-4759-a164-7680d2b3d477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670996574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2670996574
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.17749347
Short name T465
Test name
Test status
Simulation time 249459035 ps
CPU time 3.43 seconds
Started Jul 31 04:37:05 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 198444 kb
Host smart-21ec6ad7-5a25-45c5-9ff7-0eb38ec9f855
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.gpio_intr_with_filter_rand_intr_event.17749347
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.190262677
Short name T174
Test name
Test status
Simulation time 83868373 ps
CPU time 1.1 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 195852 kb
Host smart-58629b9b-645e-49ed-b479-a5a5bdcd9bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190262677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
190262677
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1165076701
Short name T642
Test name
Test status
Simulation time 65930677 ps
CPU time 1.29 seconds
Started Jul 31 04:37:03 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 198356 kb
Host smart-ecc8a037-8c14-4326-83f4-6dc77bace2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165076701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1165076701
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1603808286
Short name T513
Test name
Test status
Simulation time 31585892 ps
CPU time 1.17 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 197640 kb
Host smart-4956f592-aba6-442e-ae54-bbd8432d9abd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603808286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1603808286
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1241171633
Short name T76
Test name
Test status
Simulation time 108622979 ps
CPU time 2.66 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:03 PM PDT 24
Peak memory 198364 kb
Host smart-1be47c4d-36e9-4a2c-8548-d3aebc6cde07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241171633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1241171633
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2840309988
Short name T257
Test name
Test status
Simulation time 150531990 ps
CPU time 1.32 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 197344 kb
Host smart-84d62b2c-ce65-48b9-9775-ba9c340661e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840309988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2840309988
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3034698135
Short name T160
Test name
Test status
Simulation time 185686053 ps
CPU time 1.17 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:03 PM PDT 24
Peak memory 196260 kb
Host smart-64278245-e516-46c4-b128-feb854ffa909
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034698135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3034698135
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1347654850
Short name T9
Test name
Test status
Simulation time 15722760252 ps
CPU time 88.28 seconds
Started Jul 31 04:37:03 PM PDT 24
Finished Jul 31 04:38:31 PM PDT 24
Peak memory 198624 kb
Host smart-e5564b9a-ea58-439b-a86c-2001fa7259a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347654850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1347654850
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.598695730
Short name T614
Test name
Test status
Simulation time 34223248 ps
CPU time 0.56 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 194328 kb
Host smart-f2ec206c-8034-4f2e-bebb-f81e2ebad4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598695730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.598695730
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2675083727
Short name T227
Test name
Test status
Simulation time 83779353 ps
CPU time 0.91 seconds
Started Jul 31 04:37:04 PM PDT 24
Finished Jul 31 04:37:05 PM PDT 24
Peak memory 196296 kb
Host smart-748f6a4b-a51f-4d1a-88c7-6784c70ec1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675083727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2675083727
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1901388572
Short name T193
Test name
Test status
Simulation time 946286778 ps
CPU time 25.16 seconds
Started Jul 31 04:37:03 PM PDT 24
Finished Jul 31 04:37:28 PM PDT 24
Peak memory 195944 kb
Host smart-d1b17be5-e248-4994-8e54-f4e8c51c0c35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901388572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1901388572
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.579700916
Short name T709
Test name
Test status
Simulation time 581242803 ps
CPU time 0.78 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 196204 kb
Host smart-2aa56739-f66d-46a8-9156-d3323cab0f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579700916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.579700916
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2658891721
Short name T331
Test name
Test status
Simulation time 41280229 ps
CPU time 0.77 seconds
Started Jul 31 04:37:01 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 196080 kb
Host smart-1c781022-4ceb-4abb-bb83-eef7598b9a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658891721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2658891721
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.662093240
Short name T588
Test name
Test status
Simulation time 242662495 ps
CPU time 2.38 seconds
Started Jul 31 04:37:01 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 197580 kb
Host smart-9a261374-7a52-46b4-a338-a7c8681b7f77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662093240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.662093240
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4079298895
Short name T296
Test name
Test status
Simulation time 364737893 ps
CPU time 1.22 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 197228 kb
Host smart-a465e580-e6f5-40c3-9c7e-55152227f942
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079298895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4079298895
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1712868583
Short name T320
Test name
Test status
Simulation time 49403026 ps
CPU time 1.04 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:03 PM PDT 24
Peak memory 197108 kb
Host smart-24919283-76f5-47c0-a4cc-f2837ace244f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712868583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1712868583
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2058559073
Short name T680
Test name
Test status
Simulation time 103010062 ps
CPU time 0.67 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 194856 kb
Host smart-f30dd972-3a90-4b3f-945b-cd18c37af38d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058559073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2058559073
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1727194131
Short name T593
Test name
Test status
Simulation time 134771320 ps
CPU time 1.81 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 198388 kb
Host smart-5e9d7859-f088-43b6-98e3-4a1aa2e70636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727194131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1727194131
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2012957326
Short name T19
Test name
Test status
Simulation time 201898071 ps
CPU time 1.14 seconds
Started Jul 31 04:37:00 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 196140 kb
Host smart-cc71a87d-dc08-4aeb-a909-11f0332bdc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012957326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2012957326
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1414805044
Short name T249
Test name
Test status
Simulation time 132393251 ps
CPU time 1.31 seconds
Started Jul 31 04:37:03 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 196720 kb
Host smart-dd5dc6ef-c13c-43ce-8e3d-4dc66861670e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414805044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1414805044
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1206007225
Short name T574
Test name
Test status
Simulation time 8935254986 ps
CPU time 72.34 seconds
Started Jul 31 04:37:01 PM PDT 24
Finished Jul 31 04:38:14 PM PDT 24
Peak memory 198596 kb
Host smart-42b88e70-bfa8-4147-8c0f-203a01a9a039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206007225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1206007225
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1501939086
Short name T719
Test name
Test status
Simulation time 436820941791 ps
CPU time 2128.22 seconds
Started Jul 31 04:36:59 PM PDT 24
Finished Jul 31 05:12:28 PM PDT 24
Peak memory 198724 kb
Host smart-cd079f12-1b05-4aa9-9e35-1200ac4b5a08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1501939086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1501939086
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1450998723
Short name T662
Test name
Test status
Simulation time 36243918 ps
CPU time 0.56 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 195344 kb
Host smart-f977dd26-22dc-49b8-8d72-5ccedd8762ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450998723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1450998723
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2354758346
Short name T56
Test name
Test status
Simulation time 128419844 ps
CPU time 0.83 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 196296 kb
Host smart-c487767e-7171-4c1c-9b1f-a704ab33780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354758346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2354758346
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2167973694
Short name T540
Test name
Test status
Simulation time 263791297 ps
CPU time 13.72 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 198448 kb
Host smart-9cd377b7-2676-401d-b3d6-fa0801fa84d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167973694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2167973694
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1620274263
Short name T190
Test name
Test status
Simulation time 195653496 ps
CPU time 0.77 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:10 PM PDT 24
Peak memory 195792 kb
Host smart-aecbe1df-afb5-4df9-951b-5bc83976bf0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620274263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1620274263
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2484959774
Short name T302
Test name
Test status
Simulation time 98432642 ps
CPU time 1.35 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 197716 kb
Host smart-9014ee62-9683-41f6-9cca-d147f0bad013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484959774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2484959774
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2727086816
Short name T605
Test name
Test status
Simulation time 172460793 ps
CPU time 3.41 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 198596 kb
Host smart-af8b73f4-c30c-4f50-8a9c-1c7536746460
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727086816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2727086816
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2512522081
Short name T632
Test name
Test status
Simulation time 149956967 ps
CPU time 3.36 seconds
Started Jul 31 04:37:11 PM PDT 24
Finished Jul 31 04:37:14 PM PDT 24
Peak memory 196284 kb
Host smart-308d6925-541f-407f-829f-ee4eb7e22ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512522081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2512522081
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.87352655
Short name T634
Test name
Test status
Simulation time 32517125 ps
CPU time 1.21 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:03 PM PDT 24
Peak memory 197404 kb
Host smart-c0621feb-4a8d-47fd-8c12-04161593dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87352655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.87352655
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1468402714
Short name T671
Test name
Test status
Simulation time 22418854 ps
CPU time 0.75 seconds
Started Jul 31 04:37:05 PM PDT 24
Finished Jul 31 04:37:06 PM PDT 24
Peak memory 195392 kb
Host smart-6f07f7b2-bdb5-43e2-805c-13ab9820c175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468402714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1468402714
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.24064904
Short name T393
Test name
Test status
Simulation time 310014796 ps
CPU time 3.24 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 198384 kb
Host smart-b7349d84-9d05-4339-a25f-8aaba575aeac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand
om_long_reg_writes_reg_reads.24064904
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.93301170
Short name T428
Test name
Test status
Simulation time 82850506 ps
CPU time 1.23 seconds
Started Jul 31 04:37:02 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 195964 kb
Host smart-6d837a21-77aa-418f-98d8-3311306a1beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93301170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.93301170
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1873640845
Short name T375
Test name
Test status
Simulation time 30400574 ps
CPU time 0.76 seconds
Started Jul 31 04:37:04 PM PDT 24
Finished Jul 31 04:37:05 PM PDT 24
Peak memory 195548 kb
Host smart-380f0725-8fc6-4dee-b91a-7b4ed76eeea8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873640845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1873640845
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1307271769
Short name T413
Test name
Test status
Simulation time 8868655550 ps
CPU time 63.34 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 198668 kb
Host smart-f387f2ff-b8ec-4e55-8cb8-88bd4b8bc1de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307271769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1307271769
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.4160758052
Short name T2
Test name
Test status
Simulation time 232230644640 ps
CPU time 716.64 seconds
Started Jul 31 04:37:07 PM PDT 24
Finished Jul 31 04:49:04 PM PDT 24
Peak memory 198740 kb
Host smart-e3a436a1-d523-4f6e-931a-f6c9579da27a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4160758052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.4160758052
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2340603869
Short name T422
Test name
Test status
Simulation time 27825676 ps
CPU time 0.57 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 194984 kb
Host smart-5dfcd17f-baed-4215-b759-85284c6d6f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340603869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2340603869
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1420367206
Short name T337
Test name
Test status
Simulation time 138609173 ps
CPU time 0.81 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:08 PM PDT 24
Peak memory 195560 kb
Host smart-8b8290b6-7d4b-4994-a404-c7e90850184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420367206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1420367206
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.997510001
Short name T656
Test name
Test status
Simulation time 706890861 ps
CPU time 9.34 seconds
Started Jul 31 04:37:07 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 198372 kb
Host smart-1c765ac2-a1ba-4076-a3d7-bd34c3dfa899
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997510001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.997510001
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1686837991
Short name T604
Test name
Test status
Simulation time 253945120 ps
CPU time 0.91 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 197392 kb
Host smart-01b67966-6478-4f3d-a825-f010284b68c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686837991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1686837991
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.106831487
Short name T667
Test name
Test status
Simulation time 96581154 ps
CPU time 1.2 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 197056 kb
Host smart-9d3874a9-7b7f-4e84-b289-09384a41a39e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106831487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.106831487
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3354699030
Short name T285
Test name
Test status
Simulation time 85576679 ps
CPU time 1.74 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 198660 kb
Host smart-c152c384-42a1-4929-b174-109ef11eb0de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354699030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3354699030
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1155119031
Short name T57
Test name
Test status
Simulation time 398408127 ps
CPU time 2.79 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 197480 kb
Host smart-b2a5dac5-73bd-4fbf-b2a8-65234e6cc9ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155119031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1155119031
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3672153212
Short name T79
Test name
Test status
Simulation time 57239134 ps
CPU time 1.09 seconds
Started Jul 31 04:37:11 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 196412 kb
Host smart-c52bfe8e-36d5-4d4f-b979-3d9f304deb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672153212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3672153212
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3318142921
Short name T648
Test name
Test status
Simulation time 73005707 ps
CPU time 0.85 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:10 PM PDT 24
Peak memory 196468 kb
Host smart-e4c8b095-064f-4c38-9961-9857dcd9c1a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318142921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3318142921
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3826430230
Short name T696
Test name
Test status
Simulation time 260297397 ps
CPU time 2.76 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 198368 kb
Host smart-9df2b454-9130-441f-a808-c980535ec495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826430230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3826430230
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2561991093
Short name T611
Test name
Test status
Simulation time 420114621 ps
CPU time 1.21 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:13 PM PDT 24
Peak memory 196192 kb
Host smart-bae6f1ab-38f6-40a0-96f4-cd55c83f7f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561991093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2561991093
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2206213552
Short name T198
Test name
Test status
Simulation time 228617791 ps
CPU time 1.16 seconds
Started Jul 31 04:37:11 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 196228 kb
Host smart-dd4aec40-5803-4fd5-a6e6-5efee34ccd0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206213552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2206213552
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.341128385
Short name T615
Test name
Test status
Simulation time 2221065427 ps
CPU time 27.29 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 198604 kb
Host smart-632a65b9-2edb-40ad-8b6f-62408e513389
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341128385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.341128385
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3615793369
Short name T510
Test name
Test status
Simulation time 38566996 ps
CPU time 0.56 seconds
Started Jul 31 04:37:17 PM PDT 24
Finished Jul 31 04:37:17 PM PDT 24
Peak memory 194516 kb
Host smart-69f11978-8782-4bb8-ae14-f68b2dc454cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615793369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3615793369
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3179056685
Short name T403
Test name
Test status
Simulation time 23106670 ps
CPU time 0.79 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:10 PM PDT 24
Peak memory 196488 kb
Host smart-8de49b0c-dc47-4b16-b48c-310214ca89eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179056685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3179056685
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2766318707
Short name T409
Test name
Test status
Simulation time 1472466067 ps
CPU time 13.26 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 198388 kb
Host smart-abaa04ec-c472-42ad-aeb3-37fe4a54c892
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766318707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2766318707
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3795385863
Short name T629
Test name
Test status
Simulation time 40382835 ps
CPU time 0.72 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 195156 kb
Host smart-b64e964b-c1d9-4ec6-a75e-6bb6bcd62ae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795385863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3795385863
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3147112638
Short name T153
Test name
Test status
Simulation time 38833070 ps
CPU time 0.78 seconds
Started Jul 31 04:37:11 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 196756 kb
Host smart-6e2b39f1-1096-41ee-8695-d8a6b0d51a0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147112638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3147112638
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.757025892
Short name T664
Test name
Test status
Simulation time 190760364 ps
CPU time 1.3 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 198332 kb
Host smart-51fdb5a1-6e97-47d7-a8d1-619378d0ade6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757025892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.757025892
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1689261821
Short name T596
Test name
Test status
Simulation time 87754283 ps
CPU time 1.92 seconds
Started Jul 31 04:37:10 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 196988 kb
Host smart-963a24ff-7e92-4847-b406-28690539dfa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689261821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1689261821
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1536712833
Short name T533
Test name
Test status
Simulation time 112178124 ps
CPU time 1.19 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 197360 kb
Host smart-a3efea50-349e-4efc-8139-a48c9a39c800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536712833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1536712833
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1258618590
Short name T244
Test name
Test status
Simulation time 87813309 ps
CPU time 1 seconds
Started Jul 31 04:37:11 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 196428 kb
Host smart-8770449d-d2dd-4fce-8a25-8286e59d1826
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258618590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1258618590
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1384210532
Short name T311
Test name
Test status
Simulation time 695527255 ps
CPU time 2.38 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:11 PM PDT 24
Peak memory 198368 kb
Host smart-b0e54f67-ec77-4616-b250-7e7feb509253
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384210532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1384210532
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.4187124116
Short name T322
Test name
Test status
Simulation time 108819244 ps
CPU time 0.99 seconds
Started Jul 31 04:37:06 PM PDT 24
Finished Jul 31 04:37:07 PM PDT 24
Peak memory 196984 kb
Host smart-d7acdb14-2045-491f-a961-e05f98e3fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187124116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.4187124116
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.734268414
Short name T668
Test name
Test status
Simulation time 103240850 ps
CPU time 0.9 seconds
Started Jul 31 04:37:08 PM PDT 24
Finished Jul 31 04:37:08 PM PDT 24
Peak memory 196264 kb
Host smart-aa49e205-cd71-4be5-b92c-2e7a7e208af2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734268414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.734268414
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1132998443
Short name T406
Test name
Test status
Simulation time 2504598559 ps
CPU time 34.58 seconds
Started Jul 31 04:37:09 PM PDT 24
Finished Jul 31 04:37:43 PM PDT 24
Peak memory 198596 kb
Host smart-ee71c807-33e6-400f-8e18-86113097166b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132998443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1132998443
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.697959862
Short name T434
Test name
Test status
Simulation time 120347721 ps
CPU time 0.55 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 194484 kb
Host smart-a1c0c538-1888-43e9-81da-d4a5c5314e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697959862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.697959862
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3184970694
Short name T400
Test name
Test status
Simulation time 98313299 ps
CPU time 0.79 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:37:14 PM PDT 24
Peak memory 196500 kb
Host smart-2f2d9019-e9f4-471f-b653-d7943ddb515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184970694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3184970694
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2604813633
Short name T118
Test name
Test status
Simulation time 700486952 ps
CPU time 17.26 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 197028 kb
Host smart-232a028c-98f4-4248-b3b5-82f82d4387de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604813633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2604813633
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3269104063
Short name T293
Test name
Test status
Simulation time 82127839 ps
CPU time 0.65 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 195592 kb
Host smart-d3db75ec-bfab-433a-8c04-6710433d2892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269104063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3269104063
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4007289633
Short name T602
Test name
Test status
Simulation time 130665756 ps
CPU time 0.85 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:13 PM PDT 24
Peak memory 196092 kb
Host smart-12e873a9-f865-4ebb-9e17-abe6107189f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007289633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4007289633
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2454264626
Short name T343
Test name
Test status
Simulation time 361082171 ps
CPU time 1.07 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:37:14 PM PDT 24
Peak memory 196740 kb
Host smart-0eb92efc-f3cf-4930-b37d-c6dea1254256
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454264626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2454264626
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3946987848
Short name T14
Test name
Test status
Simulation time 69362522 ps
CPU time 2.12 seconds
Started Jul 31 04:37:18 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 197572 kb
Host smart-49650c64-3a67-4a84-9628-8463838e223e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946987848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3946987848
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.824849375
Short name T637
Test name
Test status
Simulation time 430610595 ps
CPU time 1.16 seconds
Started Jul 31 04:37:14 PM PDT 24
Finished Jul 31 04:37:15 PM PDT 24
Peak memory 196232 kb
Host smart-6f89c801-ef91-4ed3-8f3e-2bbb7a52ba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824849375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.824849375
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.249504528
Short name T551
Test name
Test status
Simulation time 232162489 ps
CPU time 1.16 seconds
Started Jul 31 04:37:14 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 197672 kb
Host smart-d6e8963d-a0e6-443d-a66c-798a43d10299
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249504528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.249504528
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.4129137858
Short name T6
Test name
Test status
Simulation time 347513279 ps
CPU time 1.72 seconds
Started Jul 31 04:37:14 PM PDT 24
Finished Jul 31 04:37:15 PM PDT 24
Peak memory 198420 kb
Host smart-d8a2e296-4902-45c9-9e00-ecff51b402f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129137858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.4129137858
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2282783389
Short name T617
Test name
Test status
Simulation time 352598352 ps
CPU time 1.2 seconds
Started Jul 31 04:37:17 PM PDT 24
Finished Jul 31 04:37:18 PM PDT 24
Peak memory 198424 kb
Host smart-ea20acb4-d2c5-4267-894a-4a2eec0dbd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282783389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2282783389
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1597902897
Short name T564
Test name
Test status
Simulation time 164363990 ps
CPU time 0.96 seconds
Started Jul 31 04:37:17 PM PDT 24
Finished Jul 31 04:37:18 PM PDT 24
Peak memory 195960 kb
Host smart-4c8ea4de-a6d9-4d82-8592-a2266a4216c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597902897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1597902897
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1846139487
Short name T536
Test name
Test status
Simulation time 32911003475 ps
CPU time 205.56 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:40:39 PM PDT 24
Peak memory 198608 kb
Host smart-4fabe79f-124b-42ad-9dc8-eb0d698df5d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846139487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1846139487
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3794304689
Short name T158
Test name
Test status
Simulation time 24488938 ps
CPU time 0.57 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:37:14 PM PDT 24
Peak memory 195208 kb
Host smart-6d925ec8-a90e-4eaf-b8f1-90138ed27b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794304689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3794304689
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.916873961
Short name T45
Test name
Test status
Simulation time 102177401 ps
CPU time 0.83 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 196808 kb
Host smart-65f840a5-1742-4f81-9b41-122d6b3a0d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916873961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.916873961
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.646140138
Short name T180
Test name
Test status
Simulation time 1672603030 ps
CPU time 9 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:24 PM PDT 24
Peak memory 197280 kb
Host smart-ca0a1ced-acc5-4787-acc3-9d990dc4e55a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646140138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.646140138
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3283414873
Short name T22
Test name
Test status
Simulation time 233189565 ps
CPU time 1.11 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:37:14 PM PDT 24
Peak memory 198280 kb
Host smart-2ecd8171-9ad3-4647-bf17-47ed3d9414cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283414873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3283414873
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.362485723
Short name T372
Test name
Test status
Simulation time 83758953 ps
CPU time 1.4 seconds
Started Jul 31 04:37:14 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 196256 kb
Host smart-3cf7325b-6e21-4570-9491-93107c2f437e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362485723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.362485723
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2650404010
Short name T493
Test name
Test status
Simulation time 261648587 ps
CPU time 2.61 seconds
Started Jul 31 04:37:18 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 198392 kb
Host smart-8fe481e9-d8f4-470c-b743-0b32599f31ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650404010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2650404010
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2724959036
Short name T718
Test name
Test status
Simulation time 106834036 ps
CPU time 3.04 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:15 PM PDT 24
Peak memory 197456 kb
Host smart-00e39aaa-a642-4753-95d8-11992e976c79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724959036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2724959036
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2064586044
Short name T624
Test name
Test status
Simulation time 64996588 ps
CPU time 1.31 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 198272 kb
Host smart-359d3ead-b2e9-444b-bbe2-7e5ac116108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064586044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2064586044
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3727476316
Short name T437
Test name
Test status
Simulation time 170240952 ps
CPU time 1.01 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 196936 kb
Host smart-79977641-17e7-4330-8171-73c141f0a52a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727476316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3727476316
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.833578305
Short name T286
Test name
Test status
Simulation time 685573810 ps
CPU time 4.19 seconds
Started Jul 31 04:37:13 PM PDT 24
Finished Jul 31 04:37:17 PM PDT 24
Peak memory 198480 kb
Host smart-f060c092-f583-49fc-bd46-12978a6a8154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833578305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.833578305
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2445582582
Short name T188
Test name
Test status
Simulation time 226641633 ps
CPU time 1.17 seconds
Started Jul 31 04:37:16 PM PDT 24
Finished Jul 31 04:37:18 PM PDT 24
Peak memory 196224 kb
Host smart-9cc5993c-125a-447c-8346-f41e77d1543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445582582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2445582582
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2969585310
Short name T549
Test name
Test status
Simulation time 45015819 ps
CPU time 0.94 seconds
Started Jul 31 04:37:14 PM PDT 24
Finished Jul 31 04:37:15 PM PDT 24
Peak memory 195968 kb
Host smart-85064781-e97b-4571-86a2-ce11f4a6f26c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969585310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2969585310
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.859954407
Short name T625
Test name
Test status
Simulation time 16170373816 ps
CPU time 157.18 seconds
Started Jul 31 04:37:14 PM PDT 24
Finished Jul 31 04:39:52 PM PDT 24
Peak memory 198540 kb
Host smart-ede9373d-4069-4c42-80df-2ea7eaeb1fad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859954407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.859954407
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.172704601
Short name T52
Test name
Test status
Simulation time 47968628 ps
CPU time 0.54 seconds
Started Jul 31 04:36:33 PM PDT 24
Finished Jul 31 04:36:34 PM PDT 24
Peak memory 194188 kb
Host smart-5a9ea749-326c-41c7-ab1a-e883c1fae569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172704601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.172704601
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1927575555
Short name T626
Test name
Test status
Simulation time 101353307 ps
CPU time 0.88 seconds
Started Jul 31 04:36:24 PM PDT 24
Finished Jul 31 04:36:25 PM PDT 24
Peak memory 197052 kb
Host smart-0c8d3435-907b-4afc-8d01-da5e018e142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927575555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1927575555
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2221007746
Short name T532
Test name
Test status
Simulation time 230039049 ps
CPU time 11.85 seconds
Started Jul 31 04:36:24 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 197320 kb
Host smart-ba06aa24-6d4a-480f-a9af-971c02355e9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221007746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2221007746
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2197536337
Short name T578
Test name
Test status
Simulation time 94380172 ps
CPU time 0.82 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:24 PM PDT 24
Peak memory 196372 kb
Host smart-0d2a8c2c-b05c-49bd-82c8-998c5b84e305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197536337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2197536337
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1345753093
Short name T440
Test name
Test status
Simulation time 70113343 ps
CPU time 1.07 seconds
Started Jul 31 04:36:22 PM PDT 24
Finished Jul 31 04:36:23 PM PDT 24
Peak memory 196520 kb
Host smart-979bd80c-9117-4b3a-99fd-15fc41474640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345753093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1345753093
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.173437505
Short name T654
Test name
Test status
Simulation time 361264753 ps
CPU time 3.47 seconds
Started Jul 31 04:36:25 PM PDT 24
Finished Jul 31 04:36:29 PM PDT 24
Peak memory 198392 kb
Host smart-95d83756-3661-4e8f-b891-02c3c0398180
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173437505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.173437505
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2108102813
Short name T354
Test name
Test status
Simulation time 199956941 ps
CPU time 1.76 seconds
Started Jul 31 04:36:21 PM PDT 24
Finished Jul 31 04:36:22 PM PDT 24
Peak memory 197172 kb
Host smart-72537a71-ad7c-415d-9687-d8b0be797c98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108102813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2108102813
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.657834484
Short name T485
Test name
Test status
Simulation time 45306492 ps
CPU time 0.94 seconds
Started Jul 31 04:36:22 PM PDT 24
Finished Jul 31 04:36:23 PM PDT 24
Peak memory 196912 kb
Host smart-d6a92940-1080-4e69-a6be-020817d34f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657834484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.657834484
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1898398984
Short name T297
Test name
Test status
Simulation time 57255187 ps
CPU time 0.62 seconds
Started Jul 31 04:36:22 PM PDT 24
Finished Jul 31 04:36:23 PM PDT 24
Peak memory 194552 kb
Host smart-8442fe7d-b324-414b-9a4e-706a211576a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898398984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1898398984
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3839275457
Short name T203
Test name
Test status
Simulation time 134608812 ps
CPU time 2.9 seconds
Started Jul 31 04:36:22 PM PDT 24
Finished Jul 31 04:36:24 PM PDT 24
Peak memory 198448 kb
Host smart-b2d4f59f-cb7c-49b6-af7f-d80b7b5b9e98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839275457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3839275457
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.347601012
Short name T53
Test name
Test status
Simulation time 39161475 ps
CPU time 0.76 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 214148 kb
Host smart-4bd5322c-41bf-416d-a345-ee13584754d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347601012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.347601012
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3974831664
Short name T565
Test name
Test status
Simulation time 90005298 ps
CPU time 0.98 seconds
Started Jul 31 04:36:26 PM PDT 24
Finished Jul 31 04:36:27 PM PDT 24
Peak memory 196084 kb
Host smart-1c672ca4-531f-45af-b98a-b8d4a0c0f45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974831664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3974831664
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3107561950
Short name T241
Test name
Test status
Simulation time 118300953 ps
CPU time 0.96 seconds
Started Jul 31 04:36:23 PM PDT 24
Finished Jul 31 04:36:24 PM PDT 24
Peak memory 195960 kb
Host smart-038b9b1c-c4de-4c81-9808-180097f53e83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107561950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3107561950
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3373414761
Short name T568
Test name
Test status
Simulation time 27414691044 ps
CPU time 128.02 seconds
Started Jul 31 04:36:25 PM PDT 24
Finished Jul 31 04:38:33 PM PDT 24
Peak memory 198600 kb
Host smart-b46bed28-842d-4fb3-a900-a1aa88b869ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373414761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3373414761
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2015034342
Short name T66
Test name
Test status
Simulation time 59138870064 ps
CPU time 731.86 seconds
Started Jul 31 04:36:32 PM PDT 24
Finished Jul 31 04:48:44 PM PDT 24
Peak memory 198664 kb
Host smart-3050c21f-8e02-4a54-a11c-20c715b1f2b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2015034342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2015034342
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2372688277
Short name T179
Test name
Test status
Simulation time 30666999 ps
CPU time 0.55 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 194260 kb
Host smart-243e9125-3053-45c5-91f3-fcbb097df3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372688277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2372688277
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3947932956
Short name T382
Test name
Test status
Simulation time 28566306 ps
CPU time 0.88 seconds
Started Jul 31 04:37:11 PM PDT 24
Finished Jul 31 04:37:12 PM PDT 24
Peak memory 197000 kb
Host smart-5dce4f49-2ff8-412e-928c-f4fc49da0f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947932956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3947932956
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3699189846
Short name T358
Test name
Test status
Simulation time 915224080 ps
CPU time 22.43 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 196820 kb
Host smart-3ee68cf1-d5e4-4ae7-b1b9-1e35e587f9da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699189846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3699189846
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3322289887
Short name T658
Test name
Test status
Simulation time 108753089 ps
CPU time 0.8 seconds
Started Jul 31 04:37:18 PM PDT 24
Finished Jul 31 04:37:18 PM PDT 24
Peak memory 196348 kb
Host smart-b6820fea-868e-403f-97bf-ec2c6c9505a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322289887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3322289887
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1778192641
Short name T127
Test name
Test status
Simulation time 91994617 ps
CPU time 0.78 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:13 PM PDT 24
Peak memory 196480 kb
Host smart-5bbd16e0-0203-42aa-88b3-8e9ca9851fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778192641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1778192641
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3575052884
Short name T618
Test name
Test status
Simulation time 120224919 ps
CPU time 1.07 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:13 PM PDT 24
Peak memory 196716 kb
Host smart-b12f8ca2-6bd0-428a-8fbf-7547a381bb8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575052884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3575052884
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1411666919
Short name T636
Test name
Test status
Simulation time 94040515 ps
CPU time 2.1 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 196572 kb
Host smart-1cb03311-1358-4f2c-8dd8-d86cf17d6b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411666919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1411666919
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3598248780
Short name T569
Test name
Test status
Simulation time 177557212 ps
CPU time 0.94 seconds
Started Jul 31 04:37:16 PM PDT 24
Finished Jul 31 04:37:17 PM PDT 24
Peak memory 196448 kb
Host smart-f0566133-ba9c-432f-bf24-490e3d9f7a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598248780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3598248780
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1809208843
Short name T612
Test name
Test status
Simulation time 222140929 ps
CPU time 1.34 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 198408 kb
Host smart-37af9dae-c6cb-46f5-9114-3d166de72153
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809208843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1809208843
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2370482979
Short name T301
Test name
Test status
Simulation time 407105229 ps
CPU time 4.46 seconds
Started Jul 31 04:37:15 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 198244 kb
Host smart-9d385511-fa21-4bb0-99ff-5eff90f6dd9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370482979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2370482979
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1493636738
Short name T137
Test name
Test status
Simulation time 192943106 ps
CPU time 1.04 seconds
Started Jul 31 04:37:16 PM PDT 24
Finished Jul 31 04:37:17 PM PDT 24
Peak memory 196776 kb
Host smart-83a50850-302b-42c4-9b07-629365587f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493636738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1493636738
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3022923693
Short name T580
Test name
Test status
Simulation time 120970080 ps
CPU time 1.03 seconds
Started Jul 31 04:37:12 PM PDT 24
Finished Jul 31 04:37:13 PM PDT 24
Peak memory 196212 kb
Host smart-8c8ba4da-40d8-4615-a47d-877b3d697647
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022923693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3022923693
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1112765290
Short name T5
Test name
Test status
Simulation time 15973449022 ps
CPU time 174.83 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:40:14 PM PDT 24
Peak memory 198592 kb
Host smart-f62ebba9-e6e8-4a10-afb5-f75c5f5deee2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112765290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1112765290
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1258644621
Short name T367
Test name
Test status
Simulation time 38445615 ps
CPU time 0.57 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 194580 kb
Host smart-27c41019-cb73-4257-9899-d964d9dcc668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258644621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1258644621
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2901860261
Short name T136
Test name
Test status
Simulation time 100715686 ps
CPU time 0.88 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 196988 kb
Host smart-d9386c3b-9b7f-4db1-86f6-206636fe5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901860261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2901860261
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1702105763
Short name T59
Test name
Test status
Simulation time 2413312069 ps
CPU time 27.62 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197088 kb
Host smart-d3383743-c036-49b6-a079-031fbcc8b990
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702105763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1702105763
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2054015363
Short name T638
Test name
Test status
Simulation time 362899002 ps
CPU time 1 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 198196 kb
Host smart-f55b9d35-2b89-46df-bb41-a65ef33b37cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054015363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2054015363
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3249742234
Short name T458
Test name
Test status
Simulation time 1328411782 ps
CPU time 1.45 seconds
Started Jul 31 04:37:22 PM PDT 24
Finished Jul 31 04:37:24 PM PDT 24
Peak memory 197556 kb
Host smart-2c0c7c17-7e64-4d4e-858c-5c7e74eaf7eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249742234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3249742234
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4024683895
Short name T265
Test name
Test status
Simulation time 94132406 ps
CPU time 2.94 seconds
Started Jul 31 04:37:23 PM PDT 24
Finished Jul 31 04:37:26 PM PDT 24
Peak memory 196816 kb
Host smart-0aec6549-5ba8-4c77-b119-ebebdadb697e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024683895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4024683895
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3440389224
Short name T657
Test name
Test status
Simulation time 122334604 ps
CPU time 3.32 seconds
Started Jul 31 04:37:23 PM PDT 24
Finished Jul 31 04:37:26 PM PDT 24
Peak memory 196252 kb
Host smart-85c4dd8c-82b3-4877-9668-236732b9d395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440389224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3440389224
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1756709408
Short name T16
Test name
Test status
Simulation time 84055214 ps
CPU time 0.95 seconds
Started Jul 31 04:37:24 PM PDT 24
Finished Jul 31 04:37:25 PM PDT 24
Peak memory 196436 kb
Host smart-1772b54a-fced-4640-8c6e-5f1a544444e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756709408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1756709408
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2013082276
Short name T253
Test name
Test status
Simulation time 76180781 ps
CPU time 0.63 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 194640 kb
Host smart-678929ef-9811-4932-9f84-c2ff670f7eae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013082276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2013082276
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.455937868
Short name T156
Test name
Test status
Simulation time 2389960669 ps
CPU time 3.37 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 198492 kb
Host smart-3b808853-a793-4436-9341-d37cf19c7789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455937868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.455937868
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1530280786
Short name T563
Test name
Test status
Simulation time 32674626 ps
CPU time 1.03 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 195984 kb
Host smart-7717e10b-9ae7-4224-99e1-28a0902d4a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530280786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1530280786
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4035655788
Short name T171
Test name
Test status
Simulation time 45709761 ps
CPU time 1.29 seconds
Started Jul 31 04:37:23 PM PDT 24
Finished Jul 31 04:37:24 PM PDT 24
Peak memory 198408 kb
Host smart-9d144989-6cab-4a0a-8177-21f71189b949
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035655788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4035655788
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1286505998
Short name T715
Test name
Test status
Simulation time 5689664739 ps
CPU time 36.04 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:57 PM PDT 24
Peak memory 198560 kb
Host smart-f3e56be6-7745-4d14-84d9-ee755c161bcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286505998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1286505998
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1107744903
Short name T530
Test name
Test status
Simulation time 14060357 ps
CPU time 0.56 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 193008 kb
Host smart-76f2725c-7244-4943-a7cb-b060e0ddc953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107744903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1107744903
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3201402283
Short name T347
Test name
Test status
Simulation time 17520851 ps
CPU time 0.62 seconds
Started Jul 31 04:37:22 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 194380 kb
Host smart-8e51d3bf-23a1-4d4c-9d42-ddf613dab72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201402283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3201402283
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2490347325
Short name T446
Test name
Test status
Simulation time 106703863 ps
CPU time 3.6 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:25 PM PDT 24
Peak memory 196280 kb
Host smart-d633f5fa-de27-4eae-8925-71ec2dc19d61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490347325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2490347325
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.87339192
Short name T150
Test name
Test status
Simulation time 149976137 ps
CPU time 0.68 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 195016 kb
Host smart-029b512d-9978-4df9-b8e7-0d394c2c5222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87339192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.87339192
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2821253989
Short name T132
Test name
Test status
Simulation time 98051671 ps
CPU time 1.4 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 198476 kb
Host smart-e26f49d2-667a-489f-9c1b-9563f9222284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821253989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2821253989
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3153831278
Short name T206
Test name
Test status
Simulation time 73717062 ps
CPU time 3.01 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:24 PM PDT 24
Peak memory 198528 kb
Host smart-9df7323c-7d5d-4f6c-8503-b109c5709c7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153831278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3153831278
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1063703017
Short name T315
Test name
Test status
Simulation time 108021789 ps
CPU time 1.41 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 196860 kb
Host smart-8a85d4d3-7508-4a95-b77f-d9d3e76ee9cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063703017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1063703017
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3772210622
Short name T270
Test name
Test status
Simulation time 32922898 ps
CPU time 1.13 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 196928 kb
Host smart-3476a836-2647-456d-b758-24a6ffce6c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772210622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3772210622
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.4256172297
Short name T487
Test name
Test status
Simulation time 84109785 ps
CPU time 0.85 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 197140 kb
Host smart-d91aa37a-9901-4d3b-893a-a87310cc78eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256172297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.4256172297
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.135980275
Short name T146
Test name
Test status
Simulation time 123815033 ps
CPU time 5.66 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 198424 kb
Host smart-23996f56-5d03-453b-b5ee-39025e5d1279
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135980275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.135980275
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.984718787
Short name T186
Test name
Test status
Simulation time 216721161 ps
CPU time 1.13 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 196240 kb
Host smart-9278f4d2-50e4-470a-a48d-dbbfbb58f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984718787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.984718787
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3156897018
Short name T408
Test name
Test status
Simulation time 367423770 ps
CPU time 1.34 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 197180 kb
Host smart-85e9a18a-764e-4b77-821c-e2957bc5a710
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156897018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3156897018
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3070205263
Short name T211
Test name
Test status
Simulation time 14865271884 ps
CPU time 101.58 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:39:02 PM PDT 24
Peak memory 198712 kb
Host smart-91b3b8c7-fffb-4549-90d9-f825bba55128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070205263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3070205263
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.806336541
Short name T427
Test name
Test status
Simulation time 41825476 ps
CPU time 0.57 seconds
Started Jul 31 04:37:22 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 195228 kb
Host smart-320421b8-f618-4d77-8e84-c4eb53084ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806336541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.806336541
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.4144583786
Short name T323
Test name
Test status
Simulation time 59847209 ps
CPU time 0.91 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 197128 kb
Host smart-8a0ada63-9e5c-441c-a766-1f0bc622fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144583786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.4144583786
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1205659437
Short name T501
Test name
Test status
Simulation time 438524118 ps
CPU time 6.03 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:26 PM PDT 24
Peak memory 195960 kb
Host smart-50bc97c7-6195-4ba7-85b1-7788fff2b4f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205659437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1205659437
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3014045290
Short name T29
Test name
Test status
Simulation time 78185959 ps
CPU time 0.86 seconds
Started Jul 31 04:37:22 PM PDT 24
Finished Jul 31 04:37:23 PM PDT 24
Peak memory 196928 kb
Host smart-3557675e-2fcb-4df9-954e-e71f4d836257
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014045290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3014045290
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2198692896
Short name T125
Test name
Test status
Simulation time 64060863 ps
CPU time 0.98 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 196176 kb
Host smart-466a2e30-ac95-4971-9429-0a4d3dfe6fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198692896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2198692896
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.829258236
Short name T166
Test name
Test status
Simulation time 92704571 ps
CPU time 3.62 seconds
Started Jul 31 04:37:23 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 198440 kb
Host smart-7bc866ca-d292-4e2d-a489-648e14397eea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829258236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.829258236
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3145420069
Short name T154
Test name
Test status
Simulation time 187368931 ps
CPU time 1.23 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 196180 kb
Host smart-55f8233a-b12f-493a-82ec-5a19ae543726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145420069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3145420069
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.475991249
Short name T711
Test name
Test status
Simulation time 33151869 ps
CPU time 1.25 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 197444 kb
Host smart-9a2b0a54-adc8-4c1d-b5a7-e1dfdeb23430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475991249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.475991249
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2467438569
Short name T162
Test name
Test status
Simulation time 259983456 ps
CPU time 1.26 seconds
Started Jul 31 04:37:22 PM PDT 24
Finished Jul 31 04:37:24 PM PDT 24
Peak memory 197264 kb
Host smart-8c2a3b70-9824-461b-af39-eb5270990497
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467438569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2467438569
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3785761562
Short name T679
Test name
Test status
Simulation time 1531286694 ps
CPU time 6.19 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 198376 kb
Host smart-0cf04f1b-ef76-44e2-9741-77411643e293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785761562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3785761562
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2638453838
Short name T369
Test name
Test status
Simulation time 120274747 ps
CPU time 1.45 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 198400 kb
Host smart-f13c92d4-67a9-4a4a-a73e-70acaca12fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638453838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2638453838
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.460621926
Short name T573
Test name
Test status
Simulation time 163143198 ps
CPU time 1.24 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 197244 kb
Host smart-0d4baa68-458d-4696-ae9f-3409e2947aeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460621926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.460621926
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3180645617
Short name T74
Test name
Test status
Simulation time 12645753159 ps
CPU time 44.88 seconds
Started Jul 31 04:37:22 PM PDT 24
Finished Jul 31 04:38:07 PM PDT 24
Peak memory 198584 kb
Host smart-9c7c1961-1372-4e9a-b49d-b81bcb63f6e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180645617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3180645617
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4146421032
Short name T450
Test name
Test status
Simulation time 117554074880 ps
CPU time 1491.28 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 05:02:12 PM PDT 24
Peak memory 198624 kb
Host smart-2016c5d2-a41a-4108-af8e-5f5e01f51fa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4146421032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4146421032
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1026733789
Short name T228
Test name
Test status
Simulation time 21743407 ps
CPU time 0.55 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 194252 kb
Host smart-0577b22a-0e50-498f-b870-c905bf30667e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026733789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1026733789
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2671854572
Short name T182
Test name
Test status
Simulation time 27323749 ps
CPU time 0.8 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 195768 kb
Host smart-d26766b7-63ce-48d9-8dfd-ee4dd372bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671854572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2671854572
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3347528854
Short name T514
Test name
Test status
Simulation time 1181060582 ps
CPU time 9.11 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:36 PM PDT 24
Peak memory 198392 kb
Host smart-a4ed1fc6-dfc9-46be-a6c6-f697345ca607
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347528854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3347528854
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.549852427
Short name T25
Test name
Test status
Simulation time 347944072 ps
CPU time 0.96 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 196944 kb
Host smart-74bc39f5-a837-4bd6-8516-fd9506573b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549852427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.549852427
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.471122855
Short name T653
Test name
Test status
Simulation time 188622960 ps
CPU time 0.98 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 197280 kb
Host smart-cd6b0425-79a3-4813-a414-f7fa279655fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471122855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.471122855
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.985902824
Short name T481
Test name
Test status
Simulation time 124550699 ps
CPU time 1.47 seconds
Started Jul 31 04:37:25 PM PDT 24
Finished Jul 31 04:37:26 PM PDT 24
Peak memory 197148 kb
Host smart-412471bd-e38d-4d1b-bbac-f9af603ffd35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985902824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.985902824
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2735590640
Short name T196
Test name
Test status
Simulation time 445446170 ps
CPU time 2.37 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:31 PM PDT 24
Peak memory 197392 kb
Host smart-f67fde25-228d-44a5-9e57-9d5964f91ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735590640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2735590640
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4176771273
Short name T619
Test name
Test status
Simulation time 27496941 ps
CPU time 0.68 seconds
Started Jul 31 04:37:19 PM PDT 24
Finished Jul 31 04:37:20 PM PDT 24
Peak memory 194704 kb
Host smart-2f22944e-e22d-4411-b86b-1ea6e58e8808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176771273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4176771273
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3917158543
Short name T425
Test name
Test status
Simulation time 19601238 ps
CPU time 0.79 seconds
Started Jul 31 04:37:21 PM PDT 24
Finished Jul 31 04:37:22 PM PDT 24
Peak memory 196868 kb
Host smart-c10d9bc8-5423-4cef-8daa-cae95b8fecc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917158543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3917158543
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1248777752
Short name T147
Test name
Test status
Simulation time 239382104 ps
CPU time 5.43 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:31 PM PDT 24
Peak memory 198324 kb
Host smart-7b666a67-e85c-4c39-bc37-bab8da2df4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248777752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1248777752
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.4230886786
Short name T554
Test name
Test status
Simulation time 63975213 ps
CPU time 1.28 seconds
Started Jul 31 04:37:20 PM PDT 24
Finished Jul 31 04:37:21 PM PDT 24
Peak memory 195928 kb
Host smart-0efd24d4-ce99-4950-a11c-6fcf7d3a7257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230886786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.4230886786
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1781383230
Short name T304
Test name
Test status
Simulation time 81672643 ps
CPU time 1.32 seconds
Started Jul 31 04:37:23 PM PDT 24
Finished Jul 31 04:37:25 PM PDT 24
Peak memory 197204 kb
Host smart-765f3c2a-c6a3-4f27-966a-674e611db6e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781383230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1781383230
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4078633386
Short name T695
Test name
Test status
Simulation time 17956838138 ps
CPU time 120.31 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:39:28 PM PDT 24
Peak memory 198624 kb
Host smart-a83c9d39-7faa-46cf-a360-90b6f15ae90b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078633386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4078633386
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1067589090
Short name T652
Test name
Test status
Simulation time 57731902 ps
CPU time 0.57 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 194276 kb
Host smart-6cf06741-a533-44a8-9b66-be78dbf20dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067589090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1067589090
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.4122874892
Short name T509
Test name
Test status
Simulation time 43226320 ps
CPU time 0.8 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 195568 kb
Host smart-7b700e3c-e127-407e-97ec-6ef093f6c008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122874892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.4122874892
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4010389373
Short name T324
Test name
Test status
Simulation time 821742415 ps
CPU time 13.53 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:41 PM PDT 24
Peak memory 197212 kb
Host smart-045105a8-948b-4aa7-be0b-0e0639a7e302
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010389373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4010389373
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.924872388
Short name T391
Test name
Test status
Simulation time 41331178 ps
CPU time 0.73 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 196896 kb
Host smart-ae37426f-67b8-4d29-91d5-dc0563f5e88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924872388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.924872388
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3612708218
Short name T462
Test name
Test status
Simulation time 58920962 ps
CPU time 1 seconds
Started Jul 31 04:37:24 PM PDT 24
Finished Jul 31 04:37:25 PM PDT 24
Peak memory 196504 kb
Host smart-1b914ede-ae1d-48aa-948e-66f0ec9e8d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612708218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3612708218
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2489349833
Short name T128
Test name
Test status
Simulation time 43588438 ps
CPU time 1.8 seconds
Started Jul 31 04:37:25 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 198680 kb
Host smart-fa64ce67-adcd-486a-bbc2-3fe4cf3007a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489349833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2489349833
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.46461434
Short name T245
Test name
Test status
Simulation time 113445070 ps
CPU time 1.91 seconds
Started Jul 31 04:37:25 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 196412 kb
Host smart-9a32e8f0-e9a5-486c-bba3-17d618f67333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46461434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.46461434
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3599904959
Short name T73
Test name
Test status
Simulation time 38053308 ps
CPU time 1.24 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 196164 kb
Host smart-f7d1aa3d-69db-47f3-b9e8-a593dc1766af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599904959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3599904959
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2544321713
Short name T121
Test name
Test status
Simulation time 141530920 ps
CPU time 1.3 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 197416 kb
Host smart-bf595c6c-7042-4136-b6b7-3a11c6583c9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544321713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2544321713
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2303657596
Short name T646
Test name
Test status
Simulation time 1225668371 ps
CPU time 3.66 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 198372 kb
Host smart-824fc17b-11de-4888-a6c8-4f9a85c42487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303657596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2303657596
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3029177059
Short name T131
Test name
Test status
Simulation time 177907456 ps
CPU time 0.97 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 196116 kb
Host smart-8a332a3a-7fa9-4dca-8f43-bf42c07ebdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029177059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3029177059
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3273555648
Short name T576
Test name
Test status
Simulation time 260685084 ps
CPU time 1 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 196036 kb
Host smart-610f355e-1cc6-419f-81ec-56c4ff5e4f04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273555648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3273555648
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3898386057
Short name T603
Test name
Test status
Simulation time 21245144076 ps
CPU time 106.24 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:39:15 PM PDT 24
Peak memory 198540 kb
Host smart-07f7e7f4-c5ad-4cbb-a93c-ee17611b8602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898386057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3898386057
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.506124154
Short name T148
Test name
Test status
Simulation time 17967741 ps
CPU time 0.57 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:26 PM PDT 24
Peak memory 194672 kb
Host smart-5fa9afb0-28e0-44eb-9698-9aeb4490c325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506124154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.506124154
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.972433698
Short name T433
Test name
Test status
Simulation time 18818887 ps
CPU time 0.74 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:28 PM PDT 24
Peak memory 194520 kb
Host smart-b5be7150-4fda-400a-9838-b1fe45357aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972433698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.972433698
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1499967115
Short name T335
Test name
Test status
Simulation time 446817199 ps
CPU time 12.47 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 197300 kb
Host smart-059ca9bb-ba9e-4b8c-b6b7-e94606aedd9e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499967115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1499967115
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.4240487811
Short name T248
Test name
Test status
Simulation time 57584686 ps
CPU time 0.91 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 196960 kb
Host smart-a496a616-9f9f-410e-a91f-ce514191c2e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240487811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.4240487811
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3857967076
Short name T213
Test name
Test status
Simulation time 164511116 ps
CPU time 1.07 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 196176 kb
Host smart-982baa0a-53dd-403b-a585-ac33de98a04a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857967076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3857967076
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3324894903
Short name T404
Test name
Test status
Simulation time 78777574 ps
CPU time 3.11 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 198460 kb
Host smart-268e733f-3292-4084-8fa5-886f01bedc42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324894903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3324894903
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.981129629
Short name T289
Test name
Test status
Simulation time 134569824 ps
CPU time 1.14 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 197744 kb
Host smart-9b100324-26c8-4550-8269-a8a79d8bfa6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981129629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
981129629
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1020441959
Short name T583
Test name
Test status
Simulation time 41430891 ps
CPU time 0.99 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 196356 kb
Host smart-8af1f819-a74a-41be-814c-6984317240a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020441959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1020441959
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3175786956
Short name T674
Test name
Test status
Simulation time 29635876 ps
CPU time 1.07 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 197532 kb
Host smart-9da4937c-0453-4e20-ad26-96c33c072cf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175786956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3175786956
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1462615211
Short name T692
Test name
Test status
Simulation time 1344412829 ps
CPU time 5 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:31 PM PDT 24
Peak memory 198380 kb
Host smart-afac8589-7be4-4f8a-a8b7-6f5c5264bd85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462615211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1462615211
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1504174202
Short name T395
Test name
Test status
Simulation time 148454781 ps
CPU time 0.92 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 196076 kb
Host smart-c483b5ce-65cb-4eb1-99fe-c1e4f3854ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504174202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1504174202
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2606130879
Short name T643
Test name
Test status
Simulation time 120244447 ps
CPU time 1.2 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 196308 kb
Host smart-9ba9cbc9-1b09-40b8-8b33-aeaf68541430
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606130879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2606130879
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.745719619
Short name T660
Test name
Test status
Simulation time 4835944701 ps
CPU time 62.46 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:38:31 PM PDT 24
Peak memory 198624 kb
Host smart-18983c72-e526-4d74-893a-6d1f55767f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745719619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.745719619
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1320259188
Short name T592
Test name
Test status
Simulation time 71082173145 ps
CPU time 302.87 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:42:29 PM PDT 24
Peak memory 198748 kb
Host smart-fe282714-1f20-4d49-9d19-aafb16995ee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1320259188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1320259188
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3937280510
Short name T173
Test name
Test status
Simulation time 26767564 ps
CPU time 0.59 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 194488 kb
Host smart-f4030074-5457-43dc-aa30-b5c95a60717c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937280510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3937280510
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.16752664
Short name T352
Test name
Test status
Simulation time 23899830 ps
CPU time 0.8 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 195792 kb
Host smart-4cc96999-7615-40a4-973c-0b8a96f67ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16752664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.16752664
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3516346903
Short name T135
Test name
Test status
Simulation time 627676046 ps
CPU time 7.98 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:34 PM PDT 24
Peak memory 197304 kb
Host smart-bf87980a-4bd2-43fe-a5e5-8f6ebd7f0aa7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516346903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3516346903
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3290119210
Short name T321
Test name
Test status
Simulation time 57359852 ps
CPU time 0.67 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:28 PM PDT 24
Peak memory 194996 kb
Host smart-49b2baad-2b11-47ef-8aaf-99ba5e8743d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290119210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3290119210
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1943757344
Short name T225
Test name
Test status
Simulation time 110464774 ps
CPU time 1.43 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 196172 kb
Host smart-07a67a2a-affc-4046-91bc-c11f34938676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943757344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1943757344
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2920183554
Short name T235
Test name
Test status
Simulation time 225540981 ps
CPU time 1.99 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 197568 kb
Host smart-c5f96215-1d28-46aa-8fb0-b44abaeec96b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920183554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2920183554
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.591810939
Short name T544
Test name
Test status
Simulation time 23963224 ps
CPU time 0.9 seconds
Started Jul 31 04:37:30 PM PDT 24
Finished Jul 31 04:37:31 PM PDT 24
Peak memory 196280 kb
Host smart-21385a68-f6bf-449b-87d9-af39d106b862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591810939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.591810939
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.989303366
Short name T491
Test name
Test status
Simulation time 40565636 ps
CPU time 1.05 seconds
Started Jul 31 04:37:28 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 196332 kb
Host smart-7bc65397-a8e3-46e2-8773-969e822981ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989303366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.989303366
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.217175575
Short name T488
Test name
Test status
Simulation time 212538078 ps
CPU time 3.76 seconds
Started Jul 31 04:37:26 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 198340 kb
Host smart-660f327a-9eec-4e40-93d6-29e70c5235dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217175575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.217175575
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.874760133
Short name T457
Test name
Test status
Simulation time 56159799 ps
CPU time 1.05 seconds
Started Jul 31 04:37:27 PM PDT 24
Finished Jul 31 04:37:29 PM PDT 24
Peak memory 195968 kb
Host smart-85674a8d-83fe-4037-b008-f6f8cce7eee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874760133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.874760133
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.898513514
Short name T644
Test name
Test status
Simulation time 40986285 ps
CPU time 0.91 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 195664 kb
Host smart-ac76304f-6a37-4108-84e4-b9fb35c5a1fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898513514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.898513514
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1288928393
Short name T702
Test name
Test status
Simulation time 4235533988 ps
CPU time 51.99 seconds
Started Jul 31 04:37:25 PM PDT 24
Finished Jul 31 04:38:17 PM PDT 24
Peak memory 198652 kb
Host smart-acf52897-3dbc-4191-ac48-d75b05213cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288928393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1288928393
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.4250725892
Short name T511
Test name
Test status
Simulation time 12842686 ps
CPU time 0.59 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 194468 kb
Host smart-d89eb3a3-669f-48fd-9b3e-f51c407b1992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250725892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4250725892
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1682611316
Short name T394
Test name
Test status
Simulation time 96525307 ps
CPU time 0.73 seconds
Started Jul 31 04:37:35 PM PDT 24
Finished Jul 31 04:37:36 PM PDT 24
Peak memory 195532 kb
Host smart-49ad93e4-b3e4-4746-bc36-74006e31f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682611316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1682611316
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1416298335
Short name T124
Test name
Test status
Simulation time 429181361 ps
CPU time 21.45 seconds
Started Jul 31 04:37:34 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197388 kb
Host smart-0d155211-2768-4cca-adeb-38275fc47fad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416298335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1416298335
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1606989493
Short name T24
Test name
Test status
Simulation time 75112764 ps
CPU time 0.83 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 196344 kb
Host smart-9307d50e-2dfb-4941-9055-110751d636f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606989493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1606989493
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.291773884
Short name T401
Test name
Test status
Simulation time 269566080 ps
CPU time 1.19 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:34 PM PDT 24
Peak memory 196220 kb
Host smart-483b390b-ce9c-4692-b81c-f9f69ddf7325
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291773884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.291773884
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1667206982
Short name T445
Test name
Test status
Simulation time 149983598 ps
CPU time 2.8 seconds
Started Jul 31 04:37:35 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 196772 kb
Host smart-5620b925-2eeb-4f81-9685-2d423873cab3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667206982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1667206982
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2713076041
Short name T641
Test name
Test status
Simulation time 40302991 ps
CPU time 1.23 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 196888 kb
Host smart-98ea7a0b-fa2f-4efe-97fb-fdd89a0cfa30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713076041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2713076041
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.999714641
Short name T252
Test name
Test status
Simulation time 45103784 ps
CPU time 0.71 seconds
Started Jul 31 04:37:36 PM PDT 24
Finished Jul 31 04:37:37 PM PDT 24
Peak memory 195756 kb
Host smart-46baa651-01d9-4b7f-a810-a93a43d06128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999714641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.999714641
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4004464725
Short name T362
Test name
Test status
Simulation time 69461052 ps
CPU time 1.28 seconds
Started Jul 31 04:37:36 PM PDT 24
Finished Jul 31 04:37:37 PM PDT 24
Peak memory 197360 kb
Host smart-0c37b34d-2ef1-43f7-99e8-821ff6ae3d98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004464725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4004464725
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2123002114
Short name T159
Test name
Test status
Simulation time 3655524891 ps
CPU time 5.81 seconds
Started Jul 31 04:37:34 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 198576 kb
Host smart-5610e026-07fc-47e7-82bb-2d7690989991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123002114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2123002114
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.33262968
Short name T169
Test name
Test status
Simulation time 67426540 ps
CPU time 1.07 seconds
Started Jul 31 04:37:29 PM PDT 24
Finished Jul 31 04:37:30 PM PDT 24
Peak memory 196732 kb
Host smart-4a1fdbd3-d2c1-4ca7-b081-7ec42abe089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33262968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.33262968
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.225787389
Short name T520
Test name
Test status
Simulation time 149948673 ps
CPU time 1.39 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:34 PM PDT 24
Peak memory 198384 kb
Host smart-6d75c0e1-67f2-4abb-8b2e-f68c3aa83f86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225787389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.225787389
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2645635860
Short name T432
Test name
Test status
Simulation time 12009007507 ps
CPU time 123.08 seconds
Started Jul 31 04:37:35 PM PDT 24
Finished Jul 31 04:39:38 PM PDT 24
Peak memory 198624 kb
Host smart-acfcb40f-ae8f-42a5-944f-b02854468ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645635860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2645635860
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.4229504753
Short name T12
Test name
Test status
Simulation time 10384622 ps
CPU time 0.57 seconds
Started Jul 31 04:37:34 PM PDT 24
Finished Jul 31 04:37:35 PM PDT 24
Peak memory 194320 kb
Host smart-b3ce5676-1738-4e9c-9492-bf7b5b1f42d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229504753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.4229504753
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3297420272
Short name T176
Test name
Test status
Simulation time 35652180 ps
CPU time 0.63 seconds
Started Jul 31 04:37:37 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 195040 kb
Host smart-b56f895c-b7f3-421e-908f-260dcb5a5bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297420272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3297420272
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.345472521
Short name T152
Test name
Test status
Simulation time 1385685060 ps
CPU time 10.43 seconds
Started Jul 31 04:37:33 PM PDT 24
Finished Jul 31 04:37:43 PM PDT 24
Peak memory 197504 kb
Host smart-92595774-6ba2-44ff-9a90-6234b6aaa68c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345472521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.345472521
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1529276093
Short name T666
Test name
Test status
Simulation time 66672741 ps
CPU time 0.89 seconds
Started Jul 31 04:37:35 PM PDT 24
Finished Jul 31 04:37:36 PM PDT 24
Peak memory 197592 kb
Host smart-0399ea4b-9103-44ff-ac7a-87e05d6906ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529276093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1529276093
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.984565403
Short name T645
Test name
Test status
Simulation time 171084461 ps
CPU time 1.26 seconds
Started Jul 31 04:37:37 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 196540 kb
Host smart-8b976591-b4a4-47b8-80fb-7fc13a17164a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984565403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.984565403
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2251125382
Short name T272
Test name
Test status
Simulation time 332660802 ps
CPU time 3.22 seconds
Started Jul 31 04:37:36 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 198368 kb
Host smart-43867be1-cc87-4bee-a323-c5d987d161db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251125382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2251125382
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1250166037
Short name T502
Test name
Test status
Simulation time 118993493 ps
CPU time 1.98 seconds
Started Jul 31 04:37:37 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 198452 kb
Host smart-4b355f62-a64e-4160-bd42-3d136f8176b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250166037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1250166037
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.344197260
Short name T306
Test name
Test status
Simulation time 47827068 ps
CPU time 1.01 seconds
Started Jul 31 04:37:33 PM PDT 24
Finished Jul 31 04:37:34 PM PDT 24
Peak memory 197256 kb
Host smart-5891d6d5-5179-435e-94aa-831fba56cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344197260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.344197260
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1339572241
Short name T274
Test name
Test status
Simulation time 38043832 ps
CPU time 0.94 seconds
Started Jul 31 04:37:33 PM PDT 24
Finished Jul 31 04:37:34 PM PDT 24
Peak memory 196156 kb
Host smart-e1f048b0-456c-48c0-922e-99e171bfa8cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339572241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1339572241
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.60620359
Short name T701
Test name
Test status
Simulation time 235174883 ps
CPU time 1.14 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 196936 kb
Host smart-58ba7b1e-e523-4f90-b2cd-24e5f03b6238
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60620359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand
om_long_reg_writes_reg_reads.60620359
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2417344482
Short name T187
Test name
Test status
Simulation time 44176136 ps
CPU time 1.1 seconds
Started Jul 31 04:37:31 PM PDT 24
Finished Jul 31 04:37:32 PM PDT 24
Peak memory 197060 kb
Host smart-0f0e111f-7f0d-477a-8d0d-d447b35c1caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417344482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2417344482
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.560065938
Short name T250
Test name
Test status
Simulation time 40660037 ps
CPU time 1.1 seconds
Started Jul 31 04:37:31 PM PDT 24
Finished Jul 31 04:37:32 PM PDT 24
Peak memory 195928 kb
Host smart-3f2b0d2c-5704-451d-9b8e-9e514e80918d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560065938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.560065938
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3933485451
Short name T649
Test name
Test status
Simulation time 23594234061 ps
CPU time 59.8 seconds
Started Jul 31 04:37:33 PM PDT 24
Finished Jul 31 04:38:33 PM PDT 24
Peak memory 198624 kb
Host smart-09eb6ae9-cab4-431d-9382-d2444f32a64e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933485451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3933485451
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1938718412
Short name T64
Test name
Test status
Simulation time 42552254620 ps
CPU time 1104.3 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:55:57 PM PDT 24
Peak memory 198408 kb
Host smart-d9bb898f-7e16-4598-824c-b6922480da09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1938718412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1938718412
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1417428244
Short name T633
Test name
Test status
Simulation time 14631977 ps
CPU time 0.63 seconds
Started Jul 31 04:36:30 PM PDT 24
Finished Jul 31 04:36:31 PM PDT 24
Peak memory 194320 kb
Host smart-73448d3d-d199-4ed6-96f5-93e2c75fbd18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417428244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1417428244
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.4176042726
Short name T524
Test name
Test status
Simulation time 612131728 ps
CPU time 0.86 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 196648 kb
Host smart-73244bb2-c53b-4f76-8191-e74e9668f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176042726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.4176042726
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3945113655
Short name T221
Test name
Test status
Simulation time 180443814 ps
CPU time 6.07 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:41 PM PDT 24
Peak memory 197380 kb
Host smart-31b562ce-939a-4070-93b4-f2e91012e886
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945113655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3945113655
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2575235726
Short name T23
Test name
Test status
Simulation time 64088272 ps
CPU time 0.9 seconds
Started Jul 31 04:36:32 PM PDT 24
Finished Jul 31 04:36:33 PM PDT 24
Peak memory 196460 kb
Host smart-91abaee6-6303-4c3a-b48d-534df6d886df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575235726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2575235726
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2462007013
Short name T431
Test name
Test status
Simulation time 174914596 ps
CPU time 1.4 seconds
Started Jul 31 04:36:32 PM PDT 24
Finished Jul 31 04:36:33 PM PDT 24
Peak memory 197284 kb
Host smart-4e24a1f9-452b-42b3-94e8-419c8a1d68c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462007013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2462007013
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3331079654
Short name T616
Test name
Test status
Simulation time 287910257 ps
CPU time 3.05 seconds
Started Jul 31 04:36:32 PM PDT 24
Finished Jul 31 04:36:35 PM PDT 24
Peak memory 198352 kb
Host smart-40eabb49-6323-4a9d-a58a-7f3313ef04a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331079654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3331079654
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.468862677
Short name T205
Test name
Test status
Simulation time 758336682 ps
CPU time 3.25 seconds
Started Jul 31 04:36:29 PM PDT 24
Finished Jul 31 04:36:33 PM PDT 24
Peak memory 197496 kb
Host smart-bd695913-cc0f-4ab4-9986-f2326fb5a855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468862677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.468862677
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.853660560
Short name T175
Test name
Test status
Simulation time 184250590 ps
CPU time 0.67 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 194632 kb
Host smart-acd0ed5a-6e8d-44b9-9f49-486f47643f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853660560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.853660560
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.447472124
Short name T334
Test name
Test status
Simulation time 177612413 ps
CPU time 1.1 seconds
Started Jul 31 04:36:31 PM PDT 24
Finished Jul 31 04:36:32 PM PDT 24
Peak memory 196360 kb
Host smart-24aa3950-eff6-4ca9-807e-7247688874e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447472124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.447472124
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2587723710
Short name T314
Test name
Test status
Simulation time 112305303 ps
CPU time 4.75 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 198212 kb
Host smart-78e01dfe-04aa-4527-80c3-9c00bb21dc57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587723710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2587723710
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.3700432338
Short name T521
Test name
Test status
Simulation time 1016826598 ps
CPU time 1.3 seconds
Started Jul 31 04:36:30 PM PDT 24
Finished Jul 31 04:36:31 PM PDT 24
Peak memory 196924 kb
Host smart-5264e1db-0fef-483b-9650-8532f59975c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700432338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3700432338
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3924274872
Short name T495
Test name
Test status
Simulation time 127569141 ps
CPU time 0.96 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:37 PM PDT 24
Peak memory 196240 kb
Host smart-1715d236-dc01-400c-98d4-0872cc5e26ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924274872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3924274872
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2259662341
Short name T309
Test name
Test status
Simulation time 12721078070 ps
CPU time 28.87 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:37:04 PM PDT 24
Peak memory 198576 kb
Host smart-acb94d22-262d-4025-9297-15fa54fad536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259662341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2259662341
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4123976063
Short name T716
Test name
Test status
Simulation time 12491855 ps
CPU time 0.58 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 194364 kb
Host smart-54882a8c-ab38-40e4-ae09-de8fed6b192c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123976063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4123976063
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1253785712
Short name T259
Test name
Test status
Simulation time 140580976 ps
CPU time 0.82 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 197420 kb
Host smart-cbd1c404-6aa1-414c-a99b-2727291563b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253785712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1253785712
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3086824249
Short name T594
Test name
Test status
Simulation time 352162575 ps
CPU time 18.13 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:57 PM PDT 24
Peak memory 197500 kb
Host smart-c9c1b689-6365-4ffe-a861-f5024c65a3f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086824249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3086824249
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1403906989
Short name T385
Test name
Test status
Simulation time 31494998 ps
CPU time 0.74 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 195960 kb
Host smart-b59067b9-83a6-4c8e-905f-5d29dde59be5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403906989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1403906989
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.847690701
Short name T360
Test name
Test status
Simulation time 160367922 ps
CPU time 1.47 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 198464 kb
Host smart-c84642cb-a3bb-4d9a-b84f-65194d06a9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847690701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.847690701
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1431373751
Short name T373
Test name
Test status
Simulation time 82937903 ps
CPU time 3.33 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:42 PM PDT 24
Peak memory 198564 kb
Host smart-0da18ee1-1390-4510-8ba3-9eef644670df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431373751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1431373751
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.206585633
Short name T380
Test name
Test status
Simulation time 381897573 ps
CPU time 2.7 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:42 PM PDT 24
Peak memory 196176 kb
Host smart-b122ecd4-667e-45e1-a689-c9ac870d7dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206585633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
206585633
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1011957927
Short name T18
Test name
Test status
Simulation time 443251757 ps
CPU time 1.23 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 197188 kb
Host smart-406400ae-cdc3-4345-a820-c8d34203e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011957927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1011957927
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2690308447
Short name T392
Test name
Test status
Simulation time 309663740 ps
CPU time 0.66 seconds
Started Jul 31 04:37:31 PM PDT 24
Finished Jul 31 04:37:32 PM PDT 24
Peak memory 195412 kb
Host smart-ded58fad-f573-4f33-84f0-e0519b8f149b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690308447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2690308447
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2082390197
Short name T405
Test name
Test status
Simulation time 52947959 ps
CPU time 2.4 seconds
Started Jul 31 04:37:40 PM PDT 24
Finished Jul 31 04:37:43 PM PDT 24
Peak memory 198100 kb
Host smart-11a31d33-e0e1-4183-9a7c-453f3667a410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082390197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2082390197
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1563400007
Short name T161
Test name
Test status
Simulation time 127327280 ps
CPU time 0.75 seconds
Started Jul 31 04:37:30 PM PDT 24
Finished Jul 31 04:37:31 PM PDT 24
Peak memory 195672 kb
Host smart-90404bd6-4d77-48ae-9e59-0cd4fd5948c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563400007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1563400007
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3967434217
Short name T339
Test name
Test status
Simulation time 40418800 ps
CPU time 1.09 seconds
Started Jul 31 04:37:32 PM PDT 24
Finished Jul 31 04:37:33 PM PDT 24
Peak memory 195592 kb
Host smart-e4a12f7c-c36a-4a3d-8c51-0ff2baa840a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967434217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3967434217
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2460815975
Short name T356
Test name
Test status
Simulation time 3958161894 ps
CPU time 28.84 seconds
Started Jul 31 04:37:40 PM PDT 24
Finished Jul 31 04:38:09 PM PDT 24
Peak memory 198516 kb
Host smart-0c2012c4-6244-48b1-a1f7-4e405fd68668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460815975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2460815975
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3982398951
Short name T263
Test name
Test status
Simulation time 41061783 ps
CPU time 0.64 seconds
Started Jul 31 04:37:44 PM PDT 24
Finished Jul 31 04:37:45 PM PDT 24
Peak memory 194320 kb
Host smart-fad22747-6b03-4058-aeac-f1f94b0819ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982398951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3982398951
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3870690824
Short name T579
Test name
Test status
Simulation time 164335591 ps
CPU time 1.02 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 197692 kb
Host smart-f663b50b-d95d-466b-9740-5e2a1136468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870690824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3870690824
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.109636389
Short name T669
Test name
Test status
Simulation time 107481391 ps
CPU time 3.41 seconds
Started Jul 31 04:37:41 PM PDT 24
Finished Jul 31 04:37:44 PM PDT 24
Peak memory 195992 kb
Host smart-d3a7a3f5-90aa-417a-9d5d-bf7023fb671e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109636389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.109636389
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.904915316
Short name T387
Test name
Test status
Simulation time 58863311 ps
CPU time 0.92 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 197524 kb
Host smart-2f98c856-c077-426f-a65a-94d9e9c631a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904915316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.904915316
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3593612877
Short name T407
Test name
Test status
Simulation time 96884927 ps
CPU time 1.01 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 196464 kb
Host smart-5c03da12-75ac-4f07-b7c0-1a4a7900ea4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593612877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3593612877
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1205404488
Short name T268
Test name
Test status
Simulation time 344528061 ps
CPU time 2.73 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:41 PM PDT 24
Peak memory 196912 kb
Host smart-39062e91-8869-4afb-bd71-cf79ea5194f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205404488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1205404488
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1281677771
Short name T183
Test name
Test status
Simulation time 136333302 ps
CPU time 0.97 seconds
Started Jul 31 04:37:37 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 195924 kb
Host smart-92612307-435a-4f77-bb27-97d0242646df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281677771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1281677771
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.303865299
Short name T155
Test name
Test status
Simulation time 285620719 ps
CPU time 0.91 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 196988 kb
Host smart-fd9ea1ba-0873-4480-a2c9-dd077014843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303865299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.303865299
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3233136856
Short name T133
Test name
Test status
Simulation time 21625239 ps
CPU time 0.65 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 195392 kb
Host smart-4bd8cb7c-48a2-4b2c-8fbb-719984a57374
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233136856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3233136856
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2761772453
Short name T129
Test name
Test status
Simulation time 158278919 ps
CPU time 5.25 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:44 PM PDT 24
Peak memory 198448 kb
Host smart-df80313e-cdaa-4d12-bfa9-2ed22f5252e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761772453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2761772453
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.445889749
Short name T681
Test name
Test status
Simulation time 76738469 ps
CPU time 0.83 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 196772 kb
Host smart-223d4a5f-d768-4395-996e-3d6c572dc638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445889749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.445889749
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2738149044
Short name T232
Test name
Test status
Simulation time 95789247 ps
CPU time 1.06 seconds
Started Jul 31 04:37:41 PM PDT 24
Finished Jul 31 04:37:42 PM PDT 24
Peak memory 196792 kb
Host smart-c83f6d67-6620-48cf-ab59-b3fa33538b4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738149044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2738149044
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.449273986
Short name T606
Test name
Test status
Simulation time 36417393942 ps
CPU time 98.16 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:39:17 PM PDT 24
Peak memory 198500 kb
Host smart-7d0ae3fe-4421-4a97-bd12-1268c5fb2be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449273986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.449273986
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1754689406
Short name T208
Test name
Test status
Simulation time 52773494 ps
CPU time 0.57 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 194240 kb
Host smart-6f0c9b91-6412-4aaf-bfca-9863e5bf14d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754689406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1754689406
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1649554591
Short name T535
Test name
Test status
Simulation time 41227890 ps
CPU time 0.87 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 195596 kb
Host smart-ffe6cd10-6cbd-4bfd-9cad-679261a77eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649554591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1649554591
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.358078412
Short name T438
Test name
Test status
Simulation time 443052619 ps
CPU time 12.19 seconds
Started Jul 31 04:37:39 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 197088 kb
Host smart-1f1acd3d-fd9b-4479-a60b-a61c641a230b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358078412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.358078412
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3454428075
Short name T531
Test name
Test status
Simulation time 183352632 ps
CPU time 0.87 seconds
Started Jul 31 04:37:40 PM PDT 24
Finished Jul 31 04:37:41 PM PDT 24
Peak memory 197456 kb
Host smart-fe54d6f5-ef35-4c66-89c4-f29f13fd0c05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454428075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3454428075
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.123859383
Short name T144
Test name
Test status
Simulation time 43438428 ps
CPU time 0.64 seconds
Started Jul 31 04:37:42 PM PDT 24
Finished Jul 31 04:37:42 PM PDT 24
Peak memory 195448 kb
Host smart-11de3384-b4b8-4266-9ecc-a9e2bed7b8ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123859383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.123859383
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2656243370
Short name T177
Test name
Test status
Simulation time 53346543 ps
CPU time 2.08 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 198444 kb
Host smart-40bfb184-d7c1-41f4-8da8-3c44cae1c38c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656243370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2656243370
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1246694975
Short name T515
Test name
Test status
Simulation time 118113566 ps
CPU time 1.06 seconds
Started Jul 31 04:37:36 PM PDT 24
Finished Jul 31 04:37:38 PM PDT 24
Peak memory 196804 kb
Host smart-13443aa8-be43-464b-97e9-55fd675fae3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246694975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1246694975
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.180449817
Short name T684
Test name
Test status
Simulation time 59541030 ps
CPU time 1.28 seconds
Started Jul 31 04:37:38 PM PDT 24
Finished Jul 31 04:37:40 PM PDT 24
Peak memory 197056 kb
Host smart-a16b2442-986a-40d3-93cf-b6b11e00575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180449817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.180449817
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1747265225
Short name T237
Test name
Test status
Simulation time 37492859 ps
CPU time 1.27 seconds
Started Jul 31 04:37:40 PM PDT 24
Finished Jul 31 04:37:41 PM PDT 24
Peak memory 197356 kb
Host smart-003b968f-8892-4857-915a-3c4f1ec3f6db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747265225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1747265225
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2843024324
Short name T78
Test name
Test status
Simulation time 1979243629 ps
CPU time 1.86 seconds
Started Jul 31 04:37:37 PM PDT 24
Finished Jul 31 04:37:39 PM PDT 24
Peak memory 198412 kb
Host smart-3fee8744-5f27-4c6a-8e8e-b3edcecdf328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843024324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2843024324
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2651610191
Short name T217
Test name
Test status
Simulation time 104388776 ps
CPU time 1.43 seconds
Started Jul 31 04:37:41 PM PDT 24
Finished Jul 31 04:37:42 PM PDT 24
Peak memory 198496 kb
Host smart-1224c849-e6b9-475c-a234-c094e9ea2f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651610191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2651610191
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1182259325
Short name T383
Test name
Test status
Simulation time 59601513 ps
CPU time 0.73 seconds
Started Jul 31 04:37:41 PM PDT 24
Finished Jul 31 04:37:42 PM PDT 24
Peak memory 195672 kb
Host smart-6fc1efd5-f25d-4c55-80c9-6f96e212ffae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182259325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1182259325
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3538156291
Short name T499
Test name
Test status
Simulation time 22457437759 ps
CPU time 141.36 seconds
Started Jul 31 04:37:40 PM PDT 24
Finished Jul 31 04:40:01 PM PDT 24
Peak memory 198240 kb
Host smart-370a369d-b1b0-45be-88be-8a44bf8e73fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538156291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3538156291
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3544312994
Short name T572
Test name
Test status
Simulation time 37026863 ps
CPU time 0.59 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:48 PM PDT 24
Peak memory 194416 kb
Host smart-32e4154e-17bd-4d53-a758-f590ef6b95b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544312994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3544312994
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.494157813
Short name T455
Test name
Test status
Simulation time 148634567 ps
CPU time 0.69 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 196304 kb
Host smart-0542d066-6f40-436b-b8e3-6fa59a6a230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494157813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.494157813
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2717204190
Short name T319
Test name
Test status
Simulation time 1165700854 ps
CPU time 14.49 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 197512 kb
Host smart-93b6026c-04d4-4a08-8156-7b5089ebc73b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717204190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2717204190
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2197103046
Short name T567
Test name
Test status
Simulation time 194701003 ps
CPU time 0.88 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:48 PM PDT 24
Peak memory 196304 kb
Host smart-1d55813f-1799-480a-a75d-81301da95768
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197103046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2197103046
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2321395710
Short name T712
Test name
Test status
Simulation time 22709123 ps
CPU time 0.69 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 194728 kb
Host smart-178302e8-4cf0-4fea-8d82-6597f5a9b4bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321395710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2321395710
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3231284143
Short name T412
Test name
Test status
Simulation time 154242031 ps
CPU time 1.63 seconds
Started Jul 31 04:37:44 PM PDT 24
Finished Jul 31 04:37:45 PM PDT 24
Peak memory 196916 kb
Host smart-afa178a8-37a5-4a8f-b1ad-7a0b895003a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231284143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3231284143
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1907879492
Short name T500
Test name
Test status
Simulation time 79176722 ps
CPU time 1.52 seconds
Started Jul 31 04:37:43 PM PDT 24
Finished Jul 31 04:37:45 PM PDT 24
Peak memory 196408 kb
Host smart-b1ed615b-6895-419a-87af-fd997caa93ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907879492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1907879492
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2678336819
Short name T661
Test name
Test status
Simulation time 45959607 ps
CPU time 0.66 seconds
Started Jul 31 04:37:44 PM PDT 24
Finished Jul 31 04:37:45 PM PDT 24
Peak memory 194772 kb
Host smart-fa0d6ad7-9261-4671-83fa-2e1b801b8fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678336819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2678336819
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1982127972
Short name T677
Test name
Test status
Simulation time 273565832 ps
CPU time 1.08 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:49 PM PDT 24
Peak memory 196192 kb
Host smart-14e558e0-2bf3-4b5a-86e9-7f16b04774e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982127972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1982127972
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1151241575
Short name T172
Test name
Test status
Simulation time 125469471 ps
CPU time 4.2 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 198404 kb
Host smart-bed7287d-2c0d-43d8-87f5-87a835f009ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151241575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1151241575
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.631042000
Short name T683
Test name
Test status
Simulation time 66792731 ps
CPU time 0.71 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 195632 kb
Host smart-ed4426b2-37c7-48e4-b6ad-3c74687cabc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631042000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.631042000
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.129224969
Short name T298
Test name
Test status
Simulation time 193017907 ps
CPU time 1.56 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 195964 kb
Host smart-5cf949a6-630b-4d87-9aec-2a6d12188788
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129224969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.129224969
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1443624756
Short name T562
Test name
Test status
Simulation time 13372582092 ps
CPU time 32.03 seconds
Started Jul 31 04:37:54 PM PDT 24
Finished Jul 31 04:38:26 PM PDT 24
Peak memory 198604 kb
Host smart-94dbc70d-a78d-4321-892c-6dc043f4c226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443624756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1443624756
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1421751457
Short name T423
Test name
Test status
Simulation time 21116431223 ps
CPU time 591.19 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:47:37 PM PDT 24
Peak memory 198584 kb
Host smart-6d6ec901-8789-4af3-ba83-556ef13979d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1421751457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1421751457
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2549925628
Short name T529
Test name
Test status
Simulation time 15869001 ps
CPU time 0.61 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 194500 kb
Host smart-e68beca9-d7ea-4815-ab0a-d821870bbac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549925628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2549925628
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3537248593
Short name T277
Test name
Test status
Simulation time 107105143 ps
CPU time 0.83 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 195836 kb
Host smart-26b7bf4d-1e2b-47c5-ae1a-7398aa447de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537248593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3537248593
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3455783286
Short name T475
Test name
Test status
Simulation time 1477774204 ps
CPU time 13.16 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:59 PM PDT 24
Peak memory 197440 kb
Host smart-35561614-e243-4e86-9e45-fae53f32ccfb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455783286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3455783286
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3049177157
Short name T149
Test name
Test status
Simulation time 30242718 ps
CPU time 0.64 seconds
Started Jul 31 04:37:48 PM PDT 24
Finished Jul 31 04:37:49 PM PDT 24
Peak memory 194928 kb
Host smart-e5870329-471c-4649-b3b4-8c218a69e1ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049177157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3049177157
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.229822636
Short name T374
Test name
Test status
Simulation time 170497895 ps
CPU time 1.02 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 196388 kb
Host smart-f0fea6e7-17e9-4221-93e2-d92cf39f4bac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229822636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.229822636
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.835988922
Short name T27
Test name
Test status
Simulation time 429687222 ps
CPU time 2.01 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:49 PM PDT 24
Peak memory 198444 kb
Host smart-cd95a753-c4ef-48aa-a7c8-1b974f1e29c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835988922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.835988922
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2544934585
Short name T410
Test name
Test status
Simulation time 514396501 ps
CPU time 2.64 seconds
Started Jul 31 04:37:44 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 197604 kb
Host smart-c4f57810-eb1d-465b-8a10-11159bfedc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544934585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2544934585
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.278356103
Short name T442
Test name
Test status
Simulation time 32222911 ps
CPU time 1.13 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:37:47 PM PDT 24
Peak memory 197216 kb
Host smart-97fe86f4-c996-467a-9f30-7ff91477a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278356103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.278356103
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.982130167
Short name T292
Test name
Test status
Simulation time 68073067 ps
CPU time 0.78 seconds
Started Jul 31 04:37:54 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197004 kb
Host smart-66161dea-3605-4a5a-9f2e-34eedb4ef97c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982130167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.982130167
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2575533582
Short name T659
Test name
Test status
Simulation time 121450866 ps
CPU time 5.38 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 198420 kb
Host smart-5f7a5882-d05f-4a3f-8c29-8cedd73166ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575533582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2575533582
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2946839912
Short name T448
Test name
Test status
Simulation time 118475792 ps
CPU time 1.06 seconds
Started Jul 31 04:37:54 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 196200 kb
Host smart-14a972d6-8de4-4fe9-9744-180e01255c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946839912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2946839912
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2814541072
Short name T699
Test name
Test status
Simulation time 337133413 ps
CPU time 1.32 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 196044 kb
Host smart-a2c1c67b-8da8-4059-b734-28851b384b47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814541072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2814541072
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.318942549
Short name T376
Test name
Test status
Simulation time 15655187852 ps
CPU time 102.3 seconds
Started Jul 31 04:37:46 PM PDT 24
Finished Jul 31 04:39:28 PM PDT 24
Peak memory 198608 kb
Host smart-b1a7d9e6-0bf1-4024-bdf5-c37cb98c1ced
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318942549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.318942549
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.371240795
Short name T585
Test name
Test status
Simulation time 31852978177 ps
CPU time 496.32 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:46:01 PM PDT 24
Peak memory 198712 kb
Host smart-0641214e-7d45-4c3b-bb16-f6c449a5211a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=371240795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.371240795
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3142030194
Short name T41
Test name
Test status
Simulation time 19990581 ps
CPU time 0.61 seconds
Started Jul 31 04:37:53 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 194340 kb
Host smart-3d5a7bf3-283e-4888-a8b5-935c8f0b41d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142030194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3142030194
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1543405340
Short name T429
Test name
Test status
Simulation time 43509686 ps
CPU time 0.92 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:48 PM PDT 24
Peak memory 197588 kb
Host smart-d2d98506-2da7-423e-aa65-2e0c065860a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543405340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1543405340
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1247166456
Short name T219
Test name
Test status
Simulation time 176639422 ps
CPU time 9.2 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:38:00 PM PDT 24
Peak memory 197288 kb
Host smart-edf64dcd-ba43-46d1-9be8-f6e6e9c65599
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247166456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1247166456
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3628299419
Short name T230
Test name
Test status
Simulation time 128103201 ps
CPU time 0.81 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 195000 kb
Host smart-398e2ac7-b396-4d7a-bf1a-162ab32f82e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628299419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3628299419
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1044440161
Short name T327
Test name
Test status
Simulation time 84401151 ps
CPU time 1.01 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 197144 kb
Host smart-0c575c6d-fa9c-4bc4-a1a1-9e4e676dfb38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044440161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1044440161
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1841679210
Short name T523
Test name
Test status
Simulation time 127056171 ps
CPU time 2.08 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 198408 kb
Host smart-cf56d4d4-07f1-4842-b526-8c5158410a9c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841679210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1841679210
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2526206046
Short name T284
Test name
Test status
Simulation time 274114636 ps
CPU time 2.48 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 197548 kb
Host smart-049f4d52-b9ea-49dc-8d84-352838a9d192
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526206046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2526206046
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3293925208
Short name T490
Test name
Test status
Simulation time 234349422 ps
CPU time 1.24 seconds
Started Jul 31 04:37:45 PM PDT 24
Finished Jul 31 04:37:46 PM PDT 24
Peak memory 197000 kb
Host smart-550cd56a-bb77-40da-aec1-461c07e187da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293925208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3293925208
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2990193073
Short name T71
Test name
Test status
Simulation time 91883337 ps
CPU time 0.8 seconds
Started Jul 31 04:37:47 PM PDT 24
Finished Jul 31 04:37:48 PM PDT 24
Peak memory 195584 kb
Host smart-bef126e4-7fec-473a-b6d3-eecc2e44ced8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990193073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2990193073
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.844976141
Short name T620
Test name
Test status
Simulation time 2162637104 ps
CPU time 4.29 seconds
Started Jul 31 04:37:55 PM PDT 24
Finished Jul 31 04:37:59 PM PDT 24
Peak memory 198252 kb
Host smart-e2b079ba-8ed5-468b-b283-984103229d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844976141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.844976141
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3032797947
Short name T220
Test name
Test status
Simulation time 243659746 ps
CPU time 1.22 seconds
Started Jul 31 04:37:48 PM PDT 24
Finished Jul 31 04:37:49 PM PDT 24
Peak memory 197232 kb
Host smart-e433f09c-a2a7-49be-b199-e53a024da891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032797947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3032797947
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1511761162
Short name T414
Test name
Test status
Simulation time 41448946 ps
CPU time 0.9 seconds
Started Jul 31 04:37:48 PM PDT 24
Finished Jul 31 04:37:49 PM PDT 24
Peak memory 196820 kb
Host smart-516405d0-6b04-47ce-a074-5150a4c1a925
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511761162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1511761162
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4227381251
Short name T351
Test name
Test status
Simulation time 16673695616 ps
CPU time 120.47 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:39:51 PM PDT 24
Peak memory 198640 kb
Host smart-51926130-1727-4087-8f4d-8cf2b23e3c19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227381251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4227381251
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2754212512
Short name T454
Test name
Test status
Simulation time 43690592014 ps
CPU time 647.1 seconds
Started Jul 31 04:37:49 PM PDT 24
Finished Jul 31 04:48:36 PM PDT 24
Peak memory 198804 kb
Host smart-6ec3be94-83fa-45fd-8f2a-6726bbf5929d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2754212512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2754212512
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2346059088
Short name T627
Test name
Test status
Simulation time 19474035 ps
CPU time 0.57 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 194288 kb
Host smart-4ab91796-366f-4558-a973-bb8f51ba033b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346059088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2346059088
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2520043037
Short name T130
Test name
Test status
Simulation time 135873298 ps
CPU time 0.84 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 196908 kb
Host smart-1196cf2b-b8ea-4f6a-8028-23a2e71f00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520043037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2520043037
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3470853715
Short name T340
Test name
Test status
Simulation time 2796301536 ps
CPU time 23.17 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:38:14 PM PDT 24
Peak memory 197444 kb
Host smart-380b0a03-968c-4e18-a745-3313bb7434a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470853715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3470853715
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3845342164
Short name T62
Test name
Test status
Simulation time 135331355 ps
CPU time 1.01 seconds
Started Jul 31 04:37:53 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 197048 kb
Host smart-1df4acaa-d307-432d-9652-fafd7aeb266e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845342164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3845342164
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1638015553
Short name T463
Test name
Test status
Simulation time 119677449 ps
CPU time 0.65 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 195356 kb
Host smart-a5b9fc22-2caf-4cbd-9738-f892a85303d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638015553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1638015553
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1199345860
Short name T508
Test name
Test status
Simulation time 730979215 ps
CPU time 3.06 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 198512 kb
Host smart-6ad281ac-986d-423f-bda0-092305c97f7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199345860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1199345860
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1777323690
Short name T555
Test name
Test status
Simulation time 209651400 ps
CPU time 3.18 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197436 kb
Host smart-16bc7b90-b0f9-46f7-91ad-ab76a293b15a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777323690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1777323690
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1142648178
Short name T346
Test name
Test status
Simulation time 219355683 ps
CPU time 1.37 seconds
Started Jul 31 04:37:49 PM PDT 24
Finished Jul 31 04:37:50 PM PDT 24
Peak memory 197456 kb
Host smart-fa1effa5-b430-4a11-98d3-d3d00b008bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142648178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1142648178
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.585079681
Short name T377
Test name
Test status
Simulation time 55498390 ps
CPU time 0.8 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 195696 kb
Host smart-379adb01-3c6f-40d1-bdb7-f45d9355dc8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585079681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.585079681
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3539317286
Short name T710
Test name
Test status
Simulation time 2156763460 ps
CPU time 3.25 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 197548 kb
Host smart-e3f871e6-2cb7-4612-bf4b-4a741b61be0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539317286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3539317286
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1249919763
Short name T672
Test name
Test status
Simulation time 283764761 ps
CPU time 1.22 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 197072 kb
Host smart-c8955c04-c5db-43f3-ac2b-34acb900d40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249919763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1249919763
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1877379694
Short name T402
Test name
Test status
Simulation time 103118324 ps
CPU time 0.97 seconds
Started Jul 31 04:37:53 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 196936 kb
Host smart-5e4e40eb-5858-43d4-af19-0f969235c961
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877379694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1877379694
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.426469924
Short name T693
Test name
Test status
Simulation time 36550186770 ps
CPU time 125.44 seconds
Started Jul 31 04:37:55 PM PDT 24
Finished Jul 31 04:40:00 PM PDT 24
Peak memory 198304 kb
Host smart-ffa0eee9-333b-4775-b6f7-faeda49cb1ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426469924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.426469924
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3009018095
Short name T416
Test name
Test status
Simulation time 84157818711 ps
CPU time 336.22 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:43:28 PM PDT 24
Peak memory 198720 kb
Host smart-c5bea1bb-c1b2-4c5a-82cb-0ef006939371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3009018095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3009018095
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2102450362
Short name T486
Test name
Test status
Simulation time 14137413 ps
CPU time 0.58 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 194228 kb
Host smart-21eb4c6b-5806-4dce-bfff-bbe6557bfaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102450362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2102450362
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.868162353
Short name T560
Test name
Test status
Simulation time 44507899 ps
CPU time 0.72 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 195608 kb
Host smart-5b724492-ca91-4aef-b58a-9bf184ab4b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868162353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.868162353
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.631417489
Short name T303
Test name
Test status
Simulation time 656337467 ps
CPU time 19.1 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 197160 kb
Host smart-89215886-2eae-4af3-9b05-6dfb9984571d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631417489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.631417489
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2748961132
Short name T40
Test name
Test status
Simulation time 83572624 ps
CPU time 1.03 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 197116 kb
Host smart-968ec8c5-35e2-4bb1-ac05-2f6ce9b90d94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748961132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2748961132
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3638634795
Short name T243
Test name
Test status
Simulation time 214603984 ps
CPU time 1.26 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 198496 kb
Host smart-e93da1ad-507b-4656-8acb-98e7ce74b4c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638634795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3638634795
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3585364029
Short name T590
Test name
Test status
Simulation time 118763828 ps
CPU time 3.68 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197732 kb
Host smart-d3b4d571-3221-4d0f-8cfa-605619dba9b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585364029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3585364029
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.462797305
Short name T240
Test name
Test status
Simulation time 71389220 ps
CPU time 1.6 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 197200 kb
Host smart-e48d3d77-230b-414c-a6d3-e1d5988d15ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462797305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
462797305
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1315078206
Short name T591
Test name
Test status
Simulation time 285775979 ps
CPU time 1.23 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 197392 kb
Host smart-a592fb0f-1d6c-4f4e-b3bd-02a897febd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315078206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1315078206
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3265675579
Short name T246
Test name
Test status
Simulation time 278294298 ps
CPU time 0.81 seconds
Started Jul 31 04:37:51 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 195848 kb
Host smart-a00cbb1e-bfb9-43e5-aa61-2d9eb13b9eb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265675579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3265675579
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2171866636
Short name T575
Test name
Test status
Simulation time 68174858 ps
CPU time 1.48 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 198436 kb
Host smart-0c034fbd-17d8-4cf2-9ddc-07a882293851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171866636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2171866636
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3163651213
Short name T191
Test name
Test status
Simulation time 282410195 ps
CPU time 1.09 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:52 PM PDT 24
Peak memory 196176 kb
Host smart-091ef608-551e-43fc-9d66-2ae7ee9fa311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163651213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3163651213
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.645322689
Short name T705
Test name
Test status
Simulation time 151606571 ps
CPU time 1.12 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 196944 kb
Host smart-d1199dc6-1a73-4f7a-b205-6ef1865a8c24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645322689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.645322689
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2625642057
Short name T288
Test name
Test status
Simulation time 6197353857 ps
CPU time 36.48 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:38:29 PM PDT 24
Peak memory 198624 kb
Host smart-528c55fd-f019-44aa-b48b-bd79b1c35a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625642057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2625642057
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3104497182
Short name T290
Test name
Test status
Simulation time 42371162 ps
CPU time 0.59 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 195112 kb
Host smart-dd5c15ef-3b49-445c-9a0a-eea22d12e137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104497182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3104497182
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.893374185
Short name T456
Test name
Test status
Simulation time 68684346 ps
CPU time 0.72 seconds
Started Jul 31 04:37:49 PM PDT 24
Finished Jul 31 04:37:50 PM PDT 24
Peak memory 195704 kb
Host smart-ec07a89d-5ae1-456a-a3de-3b3dbf58796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893374185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.893374185
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.448237035
Short name T651
Test name
Test status
Simulation time 890568571 ps
CPU time 22.82 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 196828 kb
Host smart-d0199729-1f38-4e91-b647-6ef68d6a14b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448237035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.448237035
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.4237659225
Short name T20
Test name
Test status
Simulation time 23199768 ps
CPU time 0.61 seconds
Started Jul 31 04:37:54 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 194636 kb
Host smart-a76591ac-f674-4776-a4f9-114a62af89da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237659225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.4237659225
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3265766546
Short name T261
Test name
Test status
Simulation time 164523878 ps
CPU time 0.85 seconds
Started Jul 31 04:37:50 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 195992 kb
Host smart-7f5b7fb6-1cd0-4759-b1b4-327cc4d9328d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265766546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3265766546
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1798417105
Short name T28
Test name
Test status
Simulation time 157670822 ps
CPU time 1.63 seconds
Started Jul 31 04:37:55 PM PDT 24
Finished Jul 31 04:37:57 PM PDT 24
Peak memory 196956 kb
Host smart-6768e6d4-aac6-4a87-a5f7-09c4fa96ffe3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798417105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1798417105
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3401379578
Short name T635
Test name
Test status
Simulation time 124690615 ps
CPU time 2.75 seconds
Started Jul 31 04:37:53 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197728 kb
Host smart-a374582b-ae4e-4251-b25e-0428956c5127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401379578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3401379578
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1458260567
Short name T70
Test name
Test status
Simulation time 42049750 ps
CPU time 0.77 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 195736 kb
Host smart-2a39eec0-5773-4a11-9385-2dee65dca11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458260567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1458260567
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1945678699
Short name T11
Test name
Test status
Simulation time 19912748 ps
CPU time 0.83 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 196960 kb
Host smart-2a9e1554-51e0-4328-b31a-033f83f0bf84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945678699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1945678699
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3308130096
Short name T472
Test name
Test status
Simulation time 160957286 ps
CPU time 1.93 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:54 PM PDT 24
Peak memory 198428 kb
Host smart-eca49dcd-69a7-4dab-a259-c05b9f0bda1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308130096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3308130096
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3726465
Short name T357
Test name
Test status
Simulation time 86068002 ps
CPU time 1.13 seconds
Started Jul 31 04:37:52 PM PDT 24
Finished Jul 31 04:37:53 PM PDT 24
Peak memory 196144 kb
Host smart-1752d25e-1381-447a-9c7c-f3697313fde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3726465
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3317840676
Short name T697
Test name
Test status
Simulation time 137313307 ps
CPU time 1.26 seconds
Started Jul 31 04:37:54 PM PDT 24
Finished Jul 31 04:37:55 PM PDT 24
Peak memory 197296 kb
Host smart-1b48fa0f-885a-4893-bdc5-eb13d304acce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317840676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3317840676
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3752737889
Short name T461
Test name
Test status
Simulation time 27858900 ps
CPU time 0.6 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:00 PM PDT 24
Peak memory 194524 kb
Host smart-29b693fb-1621-42f2-9dd3-314eceb1a349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752737889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3752737889
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3316358598
Short name T224
Test name
Test status
Simulation time 80404274 ps
CPU time 0.79 seconds
Started Jul 31 04:38:00 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 195820 kb
Host smart-d4162af8-0499-444e-b107-3b7b4f89ae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316358598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3316358598
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3762566445
Short name T366
Test name
Test status
Simulation time 929454719 ps
CPU time 22.26 seconds
Started Jul 31 04:38:03 PM PDT 24
Finished Jul 31 04:38:25 PM PDT 24
Peak memory 198348 kb
Host smart-e9c8af20-d35a-41ee-b02b-373557d7e6ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762566445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3762566445
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2187369944
Short name T519
Test name
Test status
Simulation time 40385872 ps
CPU time 0.87 seconds
Started Jul 31 04:38:02 PM PDT 24
Finished Jul 31 04:38:03 PM PDT 24
Peak memory 197264 kb
Host smart-873918f3-f90c-4ea0-87b0-b7f12262d9e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187369944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2187369944
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3088920930
Short name T678
Test name
Test status
Simulation time 276595744 ps
CPU time 1.39 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:03 PM PDT 24
Peak memory 196196 kb
Host smart-f3353fb5-9047-461b-9e24-efe6b18e5851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088920930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3088920930
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3801976075
Short name T134
Test name
Test status
Simulation time 125996740 ps
CPU time 1.6 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 197256 kb
Host smart-4a004c38-3a17-45d6-ac01-ace111ed9db7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801976075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3801976075
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4217358456
Short name T473
Test name
Test status
Simulation time 271713315 ps
CPU time 1.66 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 196476 kb
Host smart-fc46a0dc-6e6c-4896-ab57-566e4115fdac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217358456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4217358456
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1028486676
Short name T344
Test name
Test status
Simulation time 84263125 ps
CPU time 0.92 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 196280 kb
Host smart-e418d1a4-0fd7-4571-be91-802aec184f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028486676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1028486676
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1300173017
Short name T525
Test name
Test status
Simulation time 46162365 ps
CPU time 0.93 seconds
Started Jul 31 04:38:02 PM PDT 24
Finished Jul 31 04:38:03 PM PDT 24
Peak memory 196372 kb
Host smart-870bed8c-711e-4673-b99f-5732e55bc4fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300173017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1300173017
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3501730253
Short name T348
Test name
Test status
Simulation time 957888629 ps
CPU time 3.12 seconds
Started Jul 31 04:38:00 PM PDT 24
Finished Jul 31 04:38:03 PM PDT 24
Peak memory 198352 kb
Host smart-1ccfe8c7-857a-4982-9117-17401c419c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501730253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3501730253
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3402306309
Short name T581
Test name
Test status
Simulation time 48280468 ps
CPU time 1.12 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 196292 kb
Host smart-b32f2e46-5e56-4b60-b4df-a9fbc2b03f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402306309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3402306309
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1424723003
Short name T214
Test name
Test status
Simulation time 116667594 ps
CPU time 1.01 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 196292 kb
Host smart-18c54726-5614-4694-b289-a6f8bc0f13f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424723003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1424723003
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1838068517
Short name T280
Test name
Test status
Simulation time 9558733075 ps
CPU time 56.55 seconds
Started Jul 31 04:38:00 PM PDT 24
Finished Jul 31 04:38:56 PM PDT 24
Peak memory 198608 kb
Host smart-f4f7cff7-00a9-44be-8680-23f2b81ced0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838068517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1838068517
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1221983124
Short name T505
Test name
Test status
Simulation time 40124922649 ps
CPU time 563.1 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:47:24 PM PDT 24
Peak memory 198684 kb
Host smart-9d076ba7-a0f6-42cb-9bc0-37fef8bdb3b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1221983124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1221983124
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2226896846
Short name T370
Test name
Test status
Simulation time 39565614 ps
CPU time 0.56 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 195220 kb
Host smart-946f56ac-8205-496d-b019-254415845be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226896846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2226896846
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4176803857
Short name T492
Test name
Test status
Simulation time 87241261 ps
CPU time 0.79 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 196420 kb
Host smart-c88cc259-9d2d-4e95-b11e-ebd9b133aaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176803857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4176803857
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2351136749
Short name T170
Test name
Test status
Simulation time 1447898974 ps
CPU time 19.42 seconds
Started Jul 31 04:36:29 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 195920 kb
Host smart-2cb956ce-c520-4dc7-906a-412b3ba8af54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351136749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2351136749
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4287813931
Short name T436
Test name
Test status
Simulation time 248729728 ps
CPU time 1.02 seconds
Started Jul 31 04:36:40 PM PDT 24
Finished Jul 31 04:36:41 PM PDT 24
Peak memory 197016 kb
Host smart-03fe6864-0131-4f9c-a223-81a230c40d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287813931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4287813931
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3065512470
Short name T556
Test name
Test status
Simulation time 508884885 ps
CPU time 0.94 seconds
Started Jul 31 04:36:30 PM PDT 24
Finished Jul 31 04:36:31 PM PDT 24
Peak memory 196196 kb
Host smart-b5920f3f-2a12-4022-a9de-327cc6a06c1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065512470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3065512470
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.181229089
Short name T299
Test name
Test status
Simulation time 84915603 ps
CPU time 3.06 seconds
Started Jul 31 04:36:30 PM PDT 24
Finished Jul 31 04:36:33 PM PDT 24
Peak memory 198484 kb
Host smart-1464401c-2a3f-4b16-a514-2694e0d15efd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181229089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.181229089
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.535645458
Short name T165
Test name
Test status
Simulation time 1040866103 ps
CPU time 2.11 seconds
Started Jul 31 04:36:32 PM PDT 24
Finished Jul 31 04:36:35 PM PDT 24
Peak memory 197168 kb
Host smart-0575cd70-4202-4948-bc9a-d0cb8ae19241
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535645458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.535645458
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2549840011
Short name T318
Test name
Test status
Simulation time 30134072 ps
CPU time 1.13 seconds
Started Jul 31 04:36:31 PM PDT 24
Finished Jul 31 04:36:33 PM PDT 24
Peak memory 197488 kb
Host smart-12099137-28a6-4475-946c-03782ec25646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549840011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2549840011
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3313952004
Short name T61
Test name
Test status
Simulation time 69303671 ps
CPU time 1.21 seconds
Started Jul 31 04:36:32 PM PDT 24
Finished Jul 31 04:36:34 PM PDT 24
Peak memory 197348 kb
Host smart-837332ca-89bf-493c-aba4-2e0d3f1eb0ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313952004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3313952004
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3624243146
Short name T4
Test name
Test status
Simulation time 380230451 ps
CPU time 1.68 seconds
Started Jul 31 04:36:30 PM PDT 24
Finished Jul 31 04:36:32 PM PDT 24
Peak memory 198356 kb
Host smart-091b70c7-51b0-485c-a031-8550cfb00406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624243146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3624243146
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2647957094
Short name T39
Test name
Test status
Simulation time 90264598 ps
CPU time 0.95 seconds
Started Jul 31 04:36:37 PM PDT 24
Finished Jul 31 04:36:38 PM PDT 24
Peak memory 215252 kb
Host smart-dfffe2f8-80d5-4653-a3dc-d81ce40f2091
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647957094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2647957094
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3494883411
Short name T545
Test name
Test status
Simulation time 94952444 ps
CPU time 0.93 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 195968 kb
Host smart-b0e169e8-5dfb-45aa-bfec-6eb98ab3657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494883411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3494883411
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2894272130
Short name T538
Test name
Test status
Simulation time 234408843 ps
CPU time 1.13 seconds
Started Jul 31 04:36:30 PM PDT 24
Finished Jul 31 04:36:31 PM PDT 24
Peak memory 196172 kb
Host smart-ecd5ea66-3e83-4b41-b323-f2f37d7fe76e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894272130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2894272130
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2000070318
Short name T184
Test name
Test status
Simulation time 38240399807 ps
CPU time 131.91 seconds
Started Jul 31 04:36:41 PM PDT 24
Finished Jul 31 04:38:53 PM PDT 24
Peak memory 198616 kb
Host smart-f6028baf-aa42-48de-af0d-5fc54477ba8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000070318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2000070318
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3666101432
Short name T60
Test name
Test status
Simulation time 11094213 ps
CPU time 0.6 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 194252 kb
Host smart-9de719df-8a7c-46fc-b5bc-b66f5e19a9d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666101432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3666101432
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3305999940
Short name T233
Test name
Test status
Simulation time 143292427 ps
CPU time 0.81 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:00 PM PDT 24
Peak memory 195780 kb
Host smart-7aa958e4-8e17-41eb-bef1-3531f32fb381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305999940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3305999940
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1297022134
Short name T469
Test name
Test status
Simulation time 687667410 ps
CPU time 23.59 seconds
Started Jul 31 04:38:03 PM PDT 24
Finished Jul 31 04:38:27 PM PDT 24
Peak memory 195840 kb
Host smart-e7f24f73-01ac-4105-96fb-a873f0bfb02c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297022134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1297022134
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2335580958
Short name T459
Test name
Test status
Simulation time 141133422 ps
CPU time 0.71 seconds
Started Jul 31 04:38:03 PM PDT 24
Finished Jul 31 04:38:04 PM PDT 24
Peak memory 194964 kb
Host smart-dff8066a-4ea7-4e3b-aea0-935d20fa37fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335580958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2335580958
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3309081755
Short name T115
Test name
Test status
Simulation time 90005475 ps
CPU time 1.31 seconds
Started Jul 31 04:37:57 PM PDT 24
Finished Jul 31 04:37:59 PM PDT 24
Peak memory 196604 kb
Host smart-531bb64c-131f-4b60-a51c-552f0a62e95a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309081755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3309081755
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3002072637
Short name T460
Test name
Test status
Simulation time 800177938 ps
CPU time 1.84 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:03 PM PDT 24
Peak memory 196996 kb
Host smart-4f2e633f-a37b-48a9-b157-bf21467f8409
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002072637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3002072637
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1294672442
Short name T178
Test name
Test status
Simulation time 590276477 ps
CPU time 3.22 seconds
Started Jul 31 04:37:58 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 197548 kb
Host smart-2217df89-c60c-4752-a44f-ee4fd4e60802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294672442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1294672442
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1962524596
Short name T468
Test name
Test status
Simulation time 259337228 ps
CPU time 1.33 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 198484 kb
Host smart-61e8ed85-c8b8-4b2e-9012-bd91edf9f0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962524596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1962524596
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.809660507
Short name T202
Test name
Test status
Simulation time 54206272 ps
CPU time 0.81 seconds
Started Jul 31 04:38:00 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 196924 kb
Host smart-e998f99b-1f68-415e-9624-4870345e235b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809660507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.809660507
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2100690763
Short name T557
Test name
Test status
Simulation time 71908859 ps
CPU time 2.73 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 198356 kb
Host smart-0ed476d8-1efe-463b-a293-6c6c08c9406c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100690763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2100690763
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.39976623
Short name T251
Test name
Test status
Simulation time 38079040 ps
CPU time 1.03 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 196004 kb
Host smart-4232f967-3c27-4079-9a24-2ef0469c4f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39976623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.39976623
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3584230219
Short name T496
Test name
Test status
Simulation time 58638454 ps
CPU time 1.21 seconds
Started Jul 31 04:37:58 PM PDT 24
Finished Jul 31 04:37:59 PM PDT 24
Peak memory 198388 kb
Host smart-bd44c7e2-cd1c-4542-9fcf-71f01adf5901
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584230219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3584230219
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1158929470
Short name T704
Test name
Test status
Simulation time 33462882711 ps
CPU time 35.95 seconds
Started Jul 31 04:38:00 PM PDT 24
Finished Jul 31 04:38:36 PM PDT 24
Peak memory 198360 kb
Host smart-8a47b73e-0721-4571-9abc-55572c5fc2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158929470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1158929470
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.4160336028
Short name T68
Test name
Test status
Simulation time 96725193534 ps
CPU time 1889.9 seconds
Started Jul 31 04:38:02 PM PDT 24
Finished Jul 31 05:09:32 PM PDT 24
Peak memory 198684 kb
Host smart-e8e45083-1870-4d56-b0c1-316c2cea7f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4160336028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.4160336028
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.657608214
Short name T447
Test name
Test status
Simulation time 12420732 ps
CPU time 0.58 seconds
Started Jul 31 04:38:07 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 194288 kb
Host smart-bcc642bc-2480-4161-a61c-e43c7195af88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657608214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.657608214
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2933054727
Short name T194
Test name
Test status
Simulation time 43502380 ps
CPU time 0.81 seconds
Started Jul 31 04:38:02 PM PDT 24
Finished Jul 31 04:38:02 PM PDT 24
Peak memory 195480 kb
Host smart-90e796d9-d6e9-4de7-91a6-1fe8b76e4a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933054727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2933054727
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1247337675
Short name T278
Test name
Test status
Simulation time 391156034 ps
CPU time 19.83 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 197588 kb
Host smart-880de485-b64f-4540-a2cc-52707217f150
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247337675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1247337675
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.769199344
Short name T310
Test name
Test status
Simulation time 59426391 ps
CPU time 0.96 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:01 PM PDT 24
Peak memory 197884 kb
Host smart-482feeb4-5847-41e0-9564-eb2d19bf2e93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769199344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.769199344
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3075425366
Short name T215
Test name
Test status
Simulation time 150359501 ps
CPU time 1.09 seconds
Started Jul 31 04:37:58 PM PDT 24
Finished Jul 31 04:38:00 PM PDT 24
Peak memory 196500 kb
Host smart-a4a7758a-df20-460c-b53a-21543742284e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075425366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3075425366
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3142072482
Short name T269
Test name
Test status
Simulation time 39404411 ps
CPU time 1.66 seconds
Started Jul 31 04:38:03 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 198376 kb
Host smart-4a04f6c1-8c5e-432e-8a97-0b11c79a5a38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142072482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3142072482
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.483745473
Short name T601
Test name
Test status
Simulation time 340073471 ps
CPU time 3.29 seconds
Started Jul 31 04:38:01 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 197024 kb
Host smart-57515376-5b66-4292-942a-0db574918e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483745473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
483745473
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2349907127
Short name T546
Test name
Test status
Simulation time 31680684 ps
CPU time 1.06 seconds
Started Jul 31 04:38:02 PM PDT 24
Finished Jul 31 04:38:03 PM PDT 24
Peak memory 196536 kb
Host smart-71925665-5c13-44b8-9a7e-6535785fecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349907127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2349907127
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.172540649
Short name T238
Test name
Test status
Simulation time 20084008 ps
CPU time 0.67 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:00 PM PDT 24
Peak memory 195512 kb
Host smart-9f3daedd-3a34-400a-b4bd-285f8c136e99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172540649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.172540649
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4108333181
Short name T359
Test name
Test status
Simulation time 1416433809 ps
CPU time 4.83 seconds
Started Jul 31 04:38:00 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 198420 kb
Host smart-2a5a72f7-87f5-4dc8-9175-a5b2932f1a9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108333181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4108333181
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.285329010
Short name T168
Test name
Test status
Simulation time 135812442 ps
CPU time 1.03 seconds
Started Jul 31 04:37:59 PM PDT 24
Finished Jul 31 04:38:00 PM PDT 24
Peak memory 196000 kb
Host smart-38acf080-2d2f-4dc8-bc39-c6ab637e0b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285329010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.285329010
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3283063517
Short name T72
Test name
Test status
Simulation time 206312858 ps
CPU time 1.11 seconds
Started Jul 31 04:37:58 PM PDT 24
Finished Jul 31 04:37:59 PM PDT 24
Peak memory 196740 kb
Host smart-2edf7e5d-9328-410a-9fb4-bf407b67f867
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283063517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3283063517
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1434470685
Short name T553
Test name
Test status
Simulation time 43991107373 ps
CPU time 191.72 seconds
Started Jul 31 04:38:02 PM PDT 24
Finished Jul 31 04:41:14 PM PDT 24
Peak memory 198512 kb
Host smart-b0ef9984-bc74-43b5-b6c8-e795eee0a450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434470685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1434470685
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.121861716
Short name T139
Test name
Test status
Simulation time 11750724 ps
CPU time 0.55 seconds
Started Jul 31 04:38:04 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 195084 kb
Host smart-dd3f7ae8-029d-49c1-925b-567fca2d32fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121861716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.121861716
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2671086192
Short name T676
Test name
Test status
Simulation time 108802635 ps
CPU time 0.8 seconds
Started Jul 31 04:38:04 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 195788 kb
Host smart-843ec2ac-25ac-410a-9757-4bb8bf26acad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671086192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2671086192
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2570931342
Short name T466
Test name
Test status
Simulation time 321147789 ps
CPU time 8.53 seconds
Started Jul 31 04:38:03 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 197372 kb
Host smart-a5bf3ca7-cc32-4cde-88ab-2c73ebeb09c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570931342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2570931342
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.934988319
Short name T368
Test name
Test status
Simulation time 80860344 ps
CPU time 0.82 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:38:11 PM PDT 24
Peak memory 196872 kb
Host smart-f113f8e3-8e1e-4745-98be-a7d47caf17aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934988319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.934988319
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.711793043
Short name T707
Test name
Test status
Simulation time 51292390 ps
CPU time 0.92 seconds
Started Jul 31 04:38:04 PM PDT 24
Finished Jul 31 04:38:06 PM PDT 24
Peak memory 197856 kb
Host smart-7ed01d56-ecaa-4bed-85a9-d2322222920f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711793043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.711793043
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2319017772
Short name T482
Test name
Test status
Simulation time 43414033 ps
CPU time 1.66 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 198644 kb
Host smart-4b69c461-b7ba-42a5-9d9b-fab50686095f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319017772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2319017772
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.51620713
Short name T151
Test name
Test status
Simulation time 107379340 ps
CPU time 1.33 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 197720 kb
Host smart-845ba885-b3a4-45d8-a24e-79ff066b1b63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51620713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.51620713
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.902339460
Short name T691
Test name
Test status
Simulation time 236567792 ps
CPU time 0.77 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 195676 kb
Host smart-a330161d-eae3-44a0-a1c4-8dce254aa9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902339460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.902339460
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.883234786
Short name T600
Test name
Test status
Simulation time 185344634 ps
CPU time 0.97 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 196144 kb
Host smart-503b2801-b98d-4d4e-87b7-89a1620205fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883234786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.883234786
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2252086203
Short name T371
Test name
Test status
Simulation time 81737428 ps
CPU time 3.47 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:38:13 PM PDT 24
Peak memory 198396 kb
Host smart-a29a14df-f930-4ae3-85ab-35113b45ceda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252086203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2252086203
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1841789894
Short name T116
Test name
Test status
Simulation time 259132046 ps
CPU time 1.08 seconds
Started Jul 31 04:38:04 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 196696 kb
Host smart-b53f6580-72a0-448d-bf6e-3a1b596fd510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841789894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1841789894
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1533525284
Short name T195
Test name
Test status
Simulation time 210084730 ps
CPU time 0.98 seconds
Started Jul 31 04:38:05 PM PDT 24
Finished Jul 31 04:38:06 PM PDT 24
Peak memory 196220 kb
Host smart-e4197958-56a8-460a-a9ac-3a9857da8f50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533525284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1533525284
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.80284593
Short name T3
Test name
Test status
Simulation time 91006403725 ps
CPU time 133.53 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:40:25 PM PDT 24
Peak memory 198576 kb
Host smart-025acd82-e3fb-4064-b8d3-4cdfeab44285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80284593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gp
io_stress_all.80284593
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.707317466
Short name T126
Test name
Test status
Simulation time 50110051 ps
CPU time 0.6 seconds
Started Jul 31 04:38:04 PM PDT 24
Finished Jul 31 04:38:05 PM PDT 24
Peak memory 195252 kb
Host smart-422db8be-bd67-47f4-82c0-fa44b7b5cc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707317466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.707317466
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1214427879
Short name T167
Test name
Test status
Simulation time 21732974 ps
CPU time 0.66 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 194412 kb
Host smart-09afc2cc-bdd2-4ad7-be8e-93a4783a74cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214427879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1214427879
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4052619515
Short name T325
Test name
Test status
Simulation time 316869926 ps
CPU time 8.23 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:14 PM PDT 24
Peak memory 197416 kb
Host smart-27e9b15e-00b0-4f37-98a7-15d9010de86d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052619515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4052619515
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2620492429
Short name T706
Test name
Test status
Simulation time 159595115 ps
CPU time 0.79 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:07 PM PDT 24
Peak memory 196992 kb
Host smart-a1f5f405-4ecb-4d81-94ae-7b9dd1e65089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620492429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2620492429
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1832327944
Short name T690
Test name
Test status
Simulation time 70413020 ps
CPU time 0.65 seconds
Started Jul 31 04:38:05 PM PDT 24
Finished Jul 31 04:38:06 PM PDT 24
Peak memory 194684 kb
Host smart-9deb38e2-2c81-4b76-818f-479216f8a2a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832327944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1832327944
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.247445170
Short name T599
Test name
Test status
Simulation time 27721859 ps
CPU time 1.18 seconds
Started Jul 31 04:38:05 PM PDT 24
Finished Jul 31 04:38:06 PM PDT 24
Peak memory 197524 kb
Host smart-ade65568-609a-4bd9-9b0b-e973967a58e7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247445170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.247445170
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4241144837
Short name T639
Test name
Test status
Simulation time 915896204 ps
CPU time 2.64 seconds
Started Jul 31 04:38:05 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 198820 kb
Host smart-c880c172-47af-49bb-9880-e28e286276f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241144837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4241144837
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4130221436
Short name T552
Test name
Test status
Simulation time 79463028 ps
CPU time 1.05 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:07 PM PDT 24
Peak memory 196356 kb
Host smart-12c37595-6e8a-47d5-b248-d4810bfe4b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130221436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4130221436
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2414479614
Short name T479
Test name
Test status
Simulation time 100093661 ps
CPU time 1.17 seconds
Started Jul 31 04:38:15 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 197452 kb
Host smart-750e5c9a-7ced-438d-bae2-babad374c830
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414479614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2414479614
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3272570713
Short name T570
Test name
Test status
Simulation time 372249545 ps
CPU time 3.41 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:11 PM PDT 24
Peak memory 198264 kb
Host smart-bae2dca6-2a17-4841-9340-d3e3601a54b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272570713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3272570713
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.80595771
Short name T566
Test name
Test status
Simulation time 54294187 ps
CPU time 1.03 seconds
Started Jul 31 04:38:20 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 195984 kb
Host smart-7c92a3ee-7e96-4336-93dd-8fa84e620446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80595771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.80595771
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.4009903037
Short name T630
Test name
Test status
Simulation time 63077760 ps
CPU time 1.13 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:07 PM PDT 24
Peak memory 196912 kb
Host smart-a53aec24-1dd2-4fa7-b383-dad56030dac5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009903037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.4009903037
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2163518839
Short name T234
Test name
Test status
Simulation time 2676114188 ps
CPU time 35.28 seconds
Started Jul 31 04:38:05 PM PDT 24
Finished Jul 31 04:38:41 PM PDT 24
Peak memory 198576 kb
Host smart-ad231a5e-aa87-46e6-9ce7-6712dda9e810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163518839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2163518839
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.965988148
Short name T316
Test name
Test status
Simulation time 50738881 ps
CPU time 0.58 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 194268 kb
Host smart-8209293b-3e1c-47e0-bec2-d8be2f8ab5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965988148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.965988148
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1433857364
Short name T390
Test name
Test status
Simulation time 15353565 ps
CPU time 0.62 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 194480 kb
Host smart-a880a0e4-fb44-40a6-85ea-885c96e553dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433857364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1433857364
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4046108653
Short name T287
Test name
Test status
Simulation time 926939575 ps
CPU time 9.38 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:24 PM PDT 24
Peak memory 196680 kb
Host smart-4bb01474-1837-4962-9f4b-8345e3147f2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046108653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4046108653
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3560609726
Short name T484
Test name
Test status
Simulation time 36840938 ps
CPU time 0.71 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 195180 kb
Host smart-e30d946a-13d6-4869-9013-f813a8918578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560609726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3560609726
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3819659869
Short name T30
Test name
Test status
Simulation time 35702748 ps
CPU time 0.71 seconds
Started Jul 31 04:38:07 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 194756 kb
Host smart-6109ba76-1207-4956-b60a-3f06ce7744e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819659869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3819659869
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.613718267
Short name T123
Test name
Test status
Simulation time 153879009 ps
CPU time 3.25 seconds
Started Jul 31 04:38:07 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 198620 kb
Host smart-23eecf0d-55d9-424e-82f8-800ad3122268
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613718267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.613718267
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.432915347
Short name T312
Test name
Test status
Simulation time 131670169 ps
CPU time 1.83 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:13 PM PDT 24
Peak memory 196628 kb
Host smart-91bf2171-7bf0-4b2e-873c-da9c3c32b598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432915347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
432915347
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2057395133
Short name T584
Test name
Test status
Simulation time 37043522 ps
CPU time 0.84 seconds
Started Jul 31 04:38:07 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 196572 kb
Host smart-892954e2-f507-4a0e-bd55-dfc9411ea3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057395133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2057395133
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.670299411
Short name T647
Test name
Test status
Simulation time 46620477 ps
CPU time 0.75 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 195784 kb
Host smart-bc73e644-1d3b-411d-a0b2-b07d2cfc5875
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670299411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.670299411
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3623052633
Short name T516
Test name
Test status
Simulation time 142229408 ps
CPU time 4.1 seconds
Started Jul 31 04:38:07 PM PDT 24
Finished Jul 31 04:38:11 PM PDT 24
Peak memory 198420 kb
Host smart-2168368e-d7fc-4ad0-898f-e109c3fc3ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623052633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3623052633
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3816646815
Short name T142
Test name
Test status
Simulation time 39852421 ps
CPU time 1.17 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:07 PM PDT 24
Peak memory 197056 kb
Host smart-d5689062-7378-4d52-9e64-1cd9e3f6a1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816646815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3816646815
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2558734788
Short name T262
Test name
Test status
Simulation time 163262853 ps
CPU time 1.45 seconds
Started Jul 31 04:38:06 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 197308 kb
Host smart-d20684f7-22a3-4f25-8b43-c67a91a42ab6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558734788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2558734788
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2246632191
Short name T361
Test name
Test status
Simulation time 20534184882 ps
CPU time 46.18 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:57 PM PDT 24
Peak memory 198580 kb
Host smart-2214e700-3424-4572-afe2-24f615d2bcd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246632191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2246632191
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.327346686
Short name T640
Test name
Test status
Simulation time 34702677670 ps
CPU time 212.4 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:41:41 PM PDT 24
Peak memory 198640 kb
Host smart-e0a4993c-60d1-4466-92c7-13604517ab23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=327346686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.327346686
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1051399115
Short name T381
Test name
Test status
Simulation time 14909620 ps
CPU time 0.58 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 194992 kb
Host smart-ab8adc1a-ee63-42bd-88b8-ae67bf3145fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051399115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1051399115
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3343317565
Short name T418
Test name
Test status
Simulation time 25331411 ps
CPU time 0.68 seconds
Started Jul 31 04:38:17 PM PDT 24
Finished Jul 31 04:38:17 PM PDT 24
Peak memory 194472 kb
Host smart-8b097872-34bc-405e-a615-91c3a8fe5fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343317565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3343317565
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.749095533
Short name T69
Test name
Test status
Simulation time 233522458 ps
CPU time 3.21 seconds
Started Jul 31 04:38:12 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 196324 kb
Host smart-d301cad1-406c-4136-b222-8b17030de4d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749095533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.749095533
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.978426936
Short name T279
Test name
Test status
Simulation time 55333630 ps
CPU time 0.84 seconds
Started Jul 31 04:38:07 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 197416 kb
Host smart-22a27bf7-6cb1-4c58-bbd7-508c163f6598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978426936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.978426936
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3465476301
Short name T212
Test name
Test status
Simulation time 24750406 ps
CPU time 0.81 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:09 PM PDT 24
Peak memory 195852 kb
Host smart-249a2d78-65ab-40e2-8f61-aae2c0498c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465476301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3465476301
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1504207049
Short name T200
Test name
Test status
Simulation time 44310882 ps
CPU time 1.68 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 196936 kb
Host smart-5ac664d4-f610-4bc1-8b8d-f47a7df0dcf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504207049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1504207049
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3917653574
Short name T415
Test name
Test status
Simulation time 284003957 ps
CPU time 3.17 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 197588 kb
Host smart-3e2dcb70-179a-4714-bdc0-6715be103aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917653574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3917653574
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3885154794
Short name T527
Test name
Test status
Simulation time 23932043 ps
CPU time 0.94 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 196380 kb
Host smart-3d43d04b-80b3-41ea-948c-0bf47c41754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885154794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3885154794
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.345235853
Short name T141
Test name
Test status
Simulation time 190783985 ps
CPU time 1.15 seconds
Started Jul 31 04:38:17 PM PDT 24
Finished Jul 31 04:38:18 PM PDT 24
Peak memory 198460 kb
Host smart-1cfa1695-6e24-43bd-8703-7ccbfaa225b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345235853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.345235853
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3506396487
Short name T7
Test name
Test status
Simulation time 1799577168 ps
CPU time 5.58 seconds
Started Jul 31 04:38:12 PM PDT 24
Finished Jul 31 04:38:18 PM PDT 24
Peak memory 198748 kb
Host smart-f08974b6-b13d-41ca-81f0-2478263a421d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506396487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3506396487
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2308054319
Short name T439
Test name
Test status
Simulation time 92840998 ps
CPU time 0.99 seconds
Started Jul 31 04:38:16 PM PDT 24
Finished Jul 31 04:38:17 PM PDT 24
Peak memory 196256 kb
Host smart-81d0d46b-a165-4529-a101-517e54b619f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308054319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2308054319
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2086971093
Short name T308
Test name
Test status
Simulation time 73677529 ps
CPU time 0.82 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:38:11 PM PDT 24
Peak memory 196380 kb
Host smart-973be791-5134-4a51-8023-5cbce61aba0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086971093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2086971093
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3500718186
Short name T266
Test name
Test status
Simulation time 10520151871 ps
CPU time 145.35 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:40:36 PM PDT 24
Peak memory 198588 kb
Host smart-ac23b070-2281-48bf-bead-ecd7f8623a32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500718186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3500718186
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2504988502
Short name T717
Test name
Test status
Simulation time 43689846 ps
CPU time 0.6 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:08 PM PDT 24
Peak memory 195152 kb
Host smart-45308fe3-cea0-482d-a5d2-15405fa86d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504988502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2504988502
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3738601439
Short name T483
Test name
Test status
Simulation time 363151514 ps
CPU time 0.87 seconds
Started Jul 31 04:38:23 PM PDT 24
Finished Jul 31 04:38:24 PM PDT 24
Peak memory 196728 kb
Host smart-df09a194-5c06-4ab7-8d9b-25df2224ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738601439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3738601439
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3619045945
Short name T199
Test name
Test status
Simulation time 3587699847 ps
CPU time 27.56 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:38 PM PDT 24
Peak memory 198544 kb
Host smart-c7c99a36-0f9c-4684-a077-6d65294f1fa6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619045945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3619045945
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1693484970
Short name T577
Test name
Test status
Simulation time 69468207 ps
CPU time 0.87 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:09 PM PDT 24
Peak memory 197060 kb
Host smart-b00e8536-5b4b-429a-8f0c-dacac3504650
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693484970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1693484970
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2480435525
Short name T384
Test name
Test status
Simulation time 34034371 ps
CPU time 0.67 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 195540 kb
Host smart-b612919b-aa72-45f5-ae08-6e6c795e20a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480435525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2480435525
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1156389708
Short name T441
Test name
Test status
Simulation time 345944773 ps
CPU time 3.61 seconds
Started Jul 31 04:38:13 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 198584 kb
Host smart-3782a6e3-7dc0-4bdf-b6ec-1eb8f849c821
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156389708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1156389708
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2411427717
Short name T426
Test name
Test status
Simulation time 42843793 ps
CPU time 1.13 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 196744 kb
Host smart-f7a279cd-aecf-4318-9d74-b3f7bbc5defd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411427717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2411427717
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.26671365
Short name T613
Test name
Test status
Simulation time 25750844 ps
CPU time 0.89 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 196412 kb
Host smart-21d33715-799d-4214-9185-84d2643ba664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26671365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.26671365
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4275335131
Short name T628
Test name
Test status
Simulation time 75719953 ps
CPU time 1.31 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 197452 kb
Host smart-5122cb59-10f8-431e-9e20-2d92d58941cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275335131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4275335131
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4212142552
Short name T694
Test name
Test status
Simulation time 45324330 ps
CPU time 1.99 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 198300 kb
Host smart-c70c3e25-bc82-42f2-8017-9c3e571204d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212142552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4212142552
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2424544334
Short name T185
Test name
Test status
Simulation time 37055684 ps
CPU time 1.04 seconds
Started Jul 31 04:38:08 PM PDT 24
Finished Jul 31 04:38:09 PM PDT 24
Peak memory 196756 kb
Host smart-5170788a-4741-49c1-919d-0a3f61d4bb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424544334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2424544334
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.130319979
Short name T435
Test name
Test status
Simulation time 154229667 ps
CPU time 0.91 seconds
Started Jul 31 04:38:13 PM PDT 24
Finished Jul 31 04:38:14 PM PDT 24
Peak memory 196232 kb
Host smart-81047b2b-40f5-440b-a223-1c940e47dd30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130319979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.130319979
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2724440542
Short name T229
Test name
Test status
Simulation time 28172477326 ps
CPU time 158.87 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:40:53 PM PDT 24
Peak memory 198560 kb
Host smart-089e2426-70f1-41e1-a597-7069e1fcd526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724440542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2724440542
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.2825147707
Short name T83
Test name
Test status
Simulation time 11731983104 ps
CPU time 271.45 seconds
Started Jul 31 04:38:17 PM PDT 24
Finished Jul 31 04:42:53 PM PDT 24
Peak memory 207040 kb
Host smart-bbd8a9a8-85fe-439e-bf2f-d44028118c9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2825147707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.2825147707
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3822261792
Short name T474
Test name
Test status
Simulation time 22482872 ps
CPU time 0.53 seconds
Started Jul 31 04:38:20 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 194288 kb
Host smart-4d535e29-31cb-495c-9a8c-112a42e3735c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822261792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3822261792
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3892937774
Short name T537
Test name
Test status
Simulation time 23188315 ps
CPU time 0.71 seconds
Started Jul 31 04:38:15 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 195672 kb
Host smart-d1f28900-bc2a-4207-9245-ca63fe2cfdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892937774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3892937774
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3095716455
Short name T197
Test name
Test status
Simulation time 5464722066 ps
CPU time 20.5 seconds
Started Jul 31 04:38:18 PM PDT 24
Finished Jul 31 04:38:39 PM PDT 24
Peak memory 196984 kb
Host smart-93f098c7-cc9e-451e-87a6-dab10f982fba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095716455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3095716455
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2668514955
Short name T506
Test name
Test status
Simulation time 43843237 ps
CPU time 0.76 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 196992 kb
Host smart-779598e4-4a88-432e-8868-095683298bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668514955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2668514955
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1744593788
Short name T682
Test name
Test status
Simulation time 76294340 ps
CPU time 0.74 seconds
Started Jul 31 04:38:12 PM PDT 24
Finished Jul 31 04:38:13 PM PDT 24
Peak memory 195956 kb
Host smart-c8391c65-b0b5-4ce3-a569-d4181779f129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744593788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1744593788
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2330056361
Short name T260
Test name
Test status
Simulation time 81391002 ps
CPU time 3.41 seconds
Started Jul 31 04:38:13 PM PDT 24
Finished Jul 31 04:38:17 PM PDT 24
Peak memory 198460 kb
Host smart-e1542e42-f039-4017-a311-d62d879519d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330056361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2330056361
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3628182765
Short name T342
Test name
Test status
Simulation time 38641185 ps
CPU time 1.09 seconds
Started Jul 31 04:38:26 PM PDT 24
Finished Jul 31 04:38:27 PM PDT 24
Peak memory 196060 kb
Host smart-ad5a9212-f364-4ef3-a960-a41c8f68ded9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628182765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3628182765
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.566090395
Short name T480
Test name
Test status
Simulation time 114797579 ps
CPU time 1.09 seconds
Started Jul 31 04:38:09 PM PDT 24
Finished Jul 31 04:38:10 PM PDT 24
Peak memory 197256 kb
Host smart-7f25c11b-2d18-45d9-a29e-f139f8d5f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566090395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.566090395
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2315668384
Short name T471
Test name
Test status
Simulation time 61216850 ps
CPU time 0.65 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:38:11 PM PDT 24
Peak memory 194540 kb
Host smart-b1517a92-0223-4266-afff-d85ebeae2ac6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315668384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2315668384
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2155396049
Short name T497
Test name
Test status
Simulation time 369981344 ps
CPU time 2.47 seconds
Started Jul 31 04:38:16 PM PDT 24
Finished Jul 31 04:38:19 PM PDT 24
Peak memory 198372 kb
Host smart-1f663032-f4c4-4960-b317-ec493ab056b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155396049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2155396049
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3494740931
Short name T548
Test name
Test status
Simulation time 230806620 ps
CPU time 1.17 seconds
Started Jul 31 04:38:23 PM PDT 24
Finished Jul 31 04:38:24 PM PDT 24
Peak memory 196252 kb
Host smart-e9df34e7-f463-4783-b413-4721fe179451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494740931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3494740931
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2087565426
Short name T386
Test name
Test status
Simulation time 293105791 ps
CPU time 1.17 seconds
Started Jul 31 04:38:15 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 195948 kb
Host smart-04db959d-186e-42d3-ac10-efdc208efcbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087565426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2087565426
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3544203431
Short name T687
Test name
Test status
Simulation time 7816551274 ps
CPU time 142.83 seconds
Started Jul 31 04:38:18 PM PDT 24
Finished Jul 31 04:40:41 PM PDT 24
Peak memory 198584 kb
Host smart-037411d1-97e9-4d36-8697-0f504cb08fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544203431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3544203431
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1149742515
Short name T8
Test name
Test status
Simulation time 21562717255 ps
CPU time 210.52 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:41:41 PM PDT 24
Peak memory 198756 kb
Host smart-db5321da-6021-4749-8356-93c0d8144271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1149742515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1149742515
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3266608753
Short name T587
Test name
Test status
Simulation time 186347990 ps
CPU time 0.54 seconds
Started Jul 31 04:38:23 PM PDT 24
Finished Jul 31 04:38:23 PM PDT 24
Peak memory 194336 kb
Host smart-4a57acbf-c53a-4512-9600-2b9b21a1d1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266608753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3266608753
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.36188220
Short name T264
Test name
Test status
Simulation time 154050249 ps
CPU time 0.93 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 196392 kb
Host smart-356e9cba-a273-41fb-bd41-6f2f4a586b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36188220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.36188220
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.423649981
Short name T294
Test name
Test status
Simulation time 713654872 ps
CPU time 23.64 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:35 PM PDT 24
Peak memory 197240 kb
Host smart-d285e5dd-8a02-41b3-bdb2-d09c6ef8cd97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423649981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.423649981
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1864810987
Short name T698
Test name
Test status
Simulation time 26643149 ps
CPU time 0.69 seconds
Started Jul 31 04:38:23 PM PDT 24
Finished Jul 31 04:38:24 PM PDT 24
Peak memory 195776 kb
Host smart-c653e86e-689e-428e-b5e3-c150ae1bc8e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864810987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1864810987
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2147037912
Short name T256
Test name
Test status
Simulation time 614850566 ps
CPU time 1 seconds
Started Jul 31 04:38:10 PM PDT 24
Finished Jul 31 04:38:11 PM PDT 24
Peak memory 196464 kb
Host smart-74300c82-46bb-4ec2-8d8c-e84453675495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147037912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2147037912
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.505667758
Short name T558
Test name
Test status
Simulation time 174871160 ps
CPU time 2.36 seconds
Started Jul 31 04:38:23 PM PDT 24
Finished Jul 31 04:38:26 PM PDT 24
Peak memory 198380 kb
Host smart-c97a6dc5-2129-4bce-a71c-c37813a42efd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505667758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.505667758
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.464365084
Short name T518
Test name
Test status
Simulation time 97993429 ps
CPU time 1.63 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 196548 kb
Host smart-c3771661-784c-488e-8515-2923671635d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464365084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
464365084
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2007582294
Short name T388
Test name
Test status
Simulation time 55875325 ps
CPU time 1.12 seconds
Started Jul 31 04:38:20 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 197132 kb
Host smart-b4ad03c6-c5b6-420e-8bc8-9f8870987210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007582294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2007582294
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1101371329
Short name T539
Test name
Test status
Simulation time 116139845 ps
CPU time 1.18 seconds
Started Jul 31 04:38:17 PM PDT 24
Finished Jul 31 04:38:18 PM PDT 24
Peak memory 196944 kb
Host smart-24c0fb92-462d-4cce-b8e2-c0195e48c527
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101371329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1101371329
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3924538927
Short name T218
Test name
Test status
Simulation time 781689041 ps
CPU time 6.26 seconds
Started Jul 31 04:38:22 PM PDT 24
Finished Jul 31 04:38:28 PM PDT 24
Peak memory 198384 kb
Host smart-8565b064-21bf-4477-8e0c-2e585f407c66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924538927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3924538927
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2056658413
Short name T631
Test name
Test status
Simulation time 150577146 ps
CPU time 1.06 seconds
Started Jul 31 04:38:13 PM PDT 24
Finished Jul 31 04:38:14 PM PDT 24
Peak memory 195972 kb
Host smart-9447697f-3a9a-47bc-896b-f22c2babad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056658413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2056658413
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4029903673
Short name T273
Test name
Test status
Simulation time 67713431 ps
CPU time 1.24 seconds
Started Jul 31 04:38:25 PM PDT 24
Finished Jul 31 04:38:27 PM PDT 24
Peak memory 198440 kb
Host smart-f5f17bc9-eec1-4067-af4f-6ebcb7916e6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029903673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4029903673
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3984730129
Short name T498
Test name
Test status
Simulation time 92026763740 ps
CPU time 187.83 seconds
Started Jul 31 04:38:21 PM PDT 24
Finished Jul 31 04:41:29 PM PDT 24
Peak memory 198576 kb
Host smart-1062037e-3678-4c4e-9147-345f79744365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984730129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3984730129
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.4065969984
Short name T329
Test name
Test status
Simulation time 57967997 ps
CPU time 0.55 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:38:12 PM PDT 24
Peak memory 194348 kb
Host smart-f7c1a23b-bbb2-4758-aa60-a86a52480c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065969984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.4065969984
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2060941293
Short name T122
Test name
Test status
Simulation time 175774359 ps
CPU time 0.8 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 196516 kb
Host smart-b3c1c572-449d-414f-8646-a6a89363447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060941293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2060941293
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.496018339
Short name T345
Test name
Test status
Simulation time 3382935124 ps
CPU time 26.93 seconds
Started Jul 31 04:38:21 PM PDT 24
Finished Jul 31 04:38:48 PM PDT 24
Peak memory 197024 kb
Host smart-2911d5de-acc8-4c0c-a4f5-d473a501cdde
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496018339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.496018339
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1214896624
Short name T247
Test name
Test status
Simulation time 407243137 ps
CPU time 0.92 seconds
Started Jul 31 04:38:16 PM PDT 24
Finished Jul 31 04:38:17 PM PDT 24
Peak memory 198088 kb
Host smart-7a844287-f7e1-42a8-b25d-f71abf410bb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214896624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1214896624
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2319644868
Short name T341
Test name
Test status
Simulation time 680992716 ps
CPU time 1.34 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 197092 kb
Host smart-0a2835d2-496a-414d-9d46-d93bff39fc39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319644868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2319644868
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.4013836380
Short name T336
Test name
Test status
Simulation time 121695999 ps
CPU time 2.47 seconds
Started Jul 31 04:38:16 PM PDT 24
Finished Jul 31 04:38:18 PM PDT 24
Peak memory 198444 kb
Host smart-e4e51d74-2761-44f1-a42f-70bfb171f253
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013836380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.4013836380
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2765315399
Short name T82
Test name
Test status
Simulation time 365082502 ps
CPU time 2.16 seconds
Started Jul 31 04:38:18 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 198436 kb
Host smart-874d543f-9cb0-4055-afe2-98f2ef43ff0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765315399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2765315399
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2216538360
Short name T477
Test name
Test status
Simulation time 48591916 ps
CPU time 0.58 seconds
Started Jul 31 04:38:22 PM PDT 24
Finished Jul 31 04:38:23 PM PDT 24
Peak memory 194608 kb
Host smart-b89f1699-c313-4ec3-b94a-0223d805359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216538360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2216538360
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3868791861
Short name T650
Test name
Test status
Simulation time 32382687 ps
CPU time 0.75 seconds
Started Jul 31 04:38:19 PM PDT 24
Finished Jul 31 04:38:19 PM PDT 24
Peak memory 196612 kb
Host smart-5ddcb109-d544-48fb-aef7-c59e677c87e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868791861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3868791861
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1317351588
Short name T608
Test name
Test status
Simulation time 1715148677 ps
CPU time 5.11 seconds
Started Jul 31 04:38:16 PM PDT 24
Finished Jul 31 04:38:21 PM PDT 24
Peak memory 198284 kb
Host smart-fe6b0e6a-71f0-400b-9281-d0703e1bb349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317351588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1317351588
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1374292914
Short name T430
Test name
Test status
Simulation time 154281542 ps
CPU time 1.37 seconds
Started Jul 31 04:38:17 PM PDT 24
Finished Jul 31 04:38:18 PM PDT 24
Peak memory 198428 kb
Host smart-ec390c74-deba-4ad2-bc9e-8b74f5aa0578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374292914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1374292914
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.80434777
Short name T164
Test name
Test status
Simulation time 130396515 ps
CPU time 0.88 seconds
Started Jul 31 04:38:14 PM PDT 24
Finished Jul 31 04:38:15 PM PDT 24
Peak memory 196640 kb
Host smart-44d9bb21-3116-4b9f-80ff-0adfd889b484
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80434777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.80434777
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3286293621
Short name T543
Test name
Test status
Simulation time 11850448726 ps
CPU time 161.53 seconds
Started Jul 31 04:38:11 PM PDT 24
Finished Jul 31 04:40:53 PM PDT 24
Peak memory 198580 kb
Host smart-834961ed-c086-49fd-a5e4-311753a907a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286293621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3286293621
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3125241078
Short name T295
Test name
Test status
Simulation time 40263630 ps
CPU time 0.56 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 194416 kb
Host smart-39874d3e-5169-422f-a97b-18bc207c9c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125241078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3125241078
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1772112376
Short name T379
Test name
Test status
Simulation time 83148839 ps
CPU time 0.94 seconds
Started Jul 31 04:36:40 PM PDT 24
Finished Jul 31 04:36:41 PM PDT 24
Peak memory 196996 kb
Host smart-94dc00ec-f759-42e1-b12d-83d2867e0706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772112376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1772112376
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4146161613
Short name T255
Test name
Test status
Simulation time 12866095836 ps
CPU time 22.79 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:37:02 PM PDT 24
Peak memory 197916 kb
Host smart-a9d97e3b-a4b7-42d1-ad5a-507bfdc1aac5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146161613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4146161613
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3446042395
Short name T81
Test name
Test status
Simulation time 234663342 ps
CPU time 0.65 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 194948 kb
Host smart-03f70be4-7fa2-4c07-a9cf-4247adabdd1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446042395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3446042395
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.290589323
Short name T271
Test name
Test status
Simulation time 647339253 ps
CPU time 1.31 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 198444 kb
Host smart-21b51d58-4e93-4c6d-b422-6c1124f5c004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290589323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.290589323
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1455184821
Short name T663
Test name
Test status
Simulation time 138270023 ps
CPU time 2.83 seconds
Started Jul 31 04:36:40 PM PDT 24
Finished Jul 31 04:36:43 PM PDT 24
Peak memory 198528 kb
Host smart-37ee4a4d-76ed-4482-8bb4-48da3c575651
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455184821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1455184821
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2628463420
Short name T714
Test name
Test status
Simulation time 170100071 ps
CPU time 3.14 seconds
Started Jul 31 04:36:40 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 197464 kb
Host smart-8dd56ce3-e051-4330-ad9f-d555866177dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628463420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2628463420
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1348247903
Short name T267
Test name
Test status
Simulation time 84264239 ps
CPU time 1.16 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 197464 kb
Host smart-f991bb93-2d23-40f5-979c-c7113fb3e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348247903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1348247903
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2729475451
Short name T157
Test name
Test status
Simulation time 106154660 ps
CPU time 0.76 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 195872 kb
Host smart-2e5709d1-8725-427e-8ed3-e326ed2236fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729475451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2729475451
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1172329320
Short name T571
Test name
Test status
Simulation time 298681553 ps
CPU time 4.53 seconds
Started Jul 31 04:36:37 PM PDT 24
Finished Jul 31 04:36:42 PM PDT 24
Peak memory 198392 kb
Host smart-8143eed1-1f52-4b18-8bcd-d74113925915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172329320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1172329320
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1718738437
Short name T464
Test name
Test status
Simulation time 669592484 ps
CPU time 1.21 seconds
Started Jul 31 04:36:37 PM PDT 24
Finished Jul 31 04:36:39 PM PDT 24
Peak memory 197204 kb
Host smart-0a45fff4-bf2d-40fd-9b84-0e9d1d751470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718738437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1718738437
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2883535888
Short name T378
Test name
Test status
Simulation time 56531318 ps
CPU time 0.92 seconds
Started Jul 31 04:36:37 PM PDT 24
Finished Jul 31 04:36:38 PM PDT 24
Peak memory 195836 kb
Host smart-20b92532-3587-4387-8d20-8dbe41cd0606
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883535888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2883535888
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3900639299
Short name T364
Test name
Test status
Simulation time 22209211621 ps
CPU time 74.03 seconds
Started Jul 31 04:36:37 PM PDT 24
Finished Jul 31 04:37:51 PM PDT 24
Peak memory 198652 kb
Host smart-3dd46509-88ad-4312-8da6-2b19c26ce997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900639299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3900639299
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.915241568
Short name T31
Test name
Test status
Simulation time 65695331262 ps
CPU time 496.05 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:44:55 PM PDT 24
Peak memory 198756 kb
Host smart-1caf756a-052d-4894-8e2e-a26dd46a7ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=915241568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.915241568
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3078420841
Short name T609
Test name
Test status
Simulation time 12659437 ps
CPU time 0.57 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 194276 kb
Host smart-af8483b3-0761-4da6-9f60-427af8174720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078420841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3078420841
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1046301416
Short name T476
Test name
Test status
Simulation time 63284001 ps
CPU time 0.75 seconds
Started Jul 31 04:36:41 PM PDT 24
Finished Jul 31 04:36:42 PM PDT 24
Peak memory 195692 kb
Host smart-23649fd6-3b34-4d33-bb19-9c0f89bff0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046301416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1046301416
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3718777355
Short name T504
Test name
Test status
Simulation time 308768168 ps
CPU time 16.99 seconds
Started Jul 31 04:36:37 PM PDT 24
Finished Jul 31 04:36:54 PM PDT 24
Peak memory 198368 kb
Host smart-74d5f3bc-6890-4c01-9552-cf12f17481c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718777355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3718777355
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.248068147
Short name T541
Test name
Test status
Simulation time 124291550 ps
CPU time 0.86 seconds
Started Jul 31 04:36:41 PM PDT 24
Finished Jul 31 04:36:42 PM PDT 24
Peak memory 196188 kb
Host smart-cb492ab4-3762-4709-a561-502c59452432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248068147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.248068147
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1272532568
Short name T223
Test name
Test status
Simulation time 75507108 ps
CPU time 0.71 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:40 PM PDT 24
Peak memory 194852 kb
Host smart-c5627e31-30ef-4163-8051-82ba535ee388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272532568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1272532568
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3973154480
Short name T589
Test name
Test status
Simulation time 128416162 ps
CPU time 1.19 seconds
Started Jul 31 04:36:38 PM PDT 24
Finished Jul 31 04:36:39 PM PDT 24
Peak memory 196920 kb
Host smart-c48382b2-fd5e-48ab-a25d-c6b321403684
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973154480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3973154480
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1466760396
Short name T512
Test name
Test status
Simulation time 183750611 ps
CPU time 1.98 seconds
Started Jul 31 04:36:40 PM PDT 24
Finished Jul 31 04:36:42 PM PDT 24
Peak memory 196408 kb
Host smart-e809731d-52cf-4cde-b431-5ba10ec01deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466760396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1466760396
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2642789369
Short name T283
Test name
Test status
Simulation time 152440665 ps
CPU time 1.24 seconds
Started Jul 31 04:36:42 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 197348 kb
Host smart-96e16002-88ba-480f-be60-889b7c0c91f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642789369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2642789369
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4161438776
Short name T420
Test name
Test status
Simulation time 106758773 ps
CPU time 1.23 seconds
Started Jul 31 04:36:38 PM PDT 24
Finished Jul 31 04:36:39 PM PDT 24
Peak memory 198388 kb
Host smart-b2535cce-3801-477d-ac04-26632a48aab1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161438776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4161438776
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.40628788
Short name T307
Test name
Test status
Simulation time 748491187 ps
CPU time 3.17 seconds
Started Jul 31 04:36:39 PM PDT 24
Finished Jul 31 04:36:42 PM PDT 24
Peak memory 198400 kb
Host smart-4ce3a4b4-aa8e-4f89-8ebb-a7f2f2813f80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rando
m_long_reg_writes_reg_reads.40628788
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1676956516
Short name T528
Test name
Test status
Simulation time 22837824 ps
CPU time 0.81 seconds
Started Jul 31 04:36:38 PM PDT 24
Finished Jul 31 04:36:39 PM PDT 24
Peak memory 196304 kb
Host smart-f77fd4c4-700e-4da5-8328-b0d97a5ec420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676956516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1676956516
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3610154667
Short name T55
Test name
Test status
Simulation time 133191793 ps
CPU time 1.19 seconds
Started Jul 31 04:36:35 PM PDT 24
Finished Jul 31 04:36:37 PM PDT 24
Peak memory 196032 kb
Host smart-25da70a1-6ed1-4ea9-b2d3-8bbbeff2ed60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610154667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3610154667
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3876886157
Short name T258
Test name
Test status
Simulation time 5777440535 ps
CPU time 157.06 seconds
Started Jul 31 04:36:41 PM PDT 24
Finished Jul 31 04:39:18 PM PDT 24
Peak memory 198552 kb
Host smart-f0729903-5705-4e54-b8c6-02b752c7d2f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876886157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3876886157
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.179008333
Short name T389
Test name
Test status
Simulation time 43724873 ps
CPU time 0.66 seconds
Started Jul 31 04:36:46 PM PDT 24
Finished Jul 31 04:36:47 PM PDT 24
Peak memory 194568 kb
Host smart-dd710cbd-7e0f-4475-8707-0d761315c149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179008333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.179008333
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3530738613
Short name T622
Test name
Test status
Simulation time 48042863 ps
CPU time 0.91 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:46 PM PDT 24
Peak memory 196792 kb
Host smart-74b80288-3f84-480c-a2e3-c4b0ce728e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530738613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3530738613
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2051131897
Short name T598
Test name
Test status
Simulation time 2108490112 ps
CPU time 17.92 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:37:01 PM PDT 24
Peak memory 196676 kb
Host smart-22052a50-3c5e-4346-810f-b687a54564a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051131897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2051131897
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4171720260
Short name T80
Test name
Test status
Simulation time 39114339 ps
CPU time 0.6 seconds
Started Jul 31 04:36:46 PM PDT 24
Finished Jul 31 04:36:47 PM PDT 24
Peak memory 194800 kb
Host smart-41c47ea2-0c27-417e-b236-96598f14213e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171720260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4171720260
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.90451110
Short name T120
Test name
Test status
Simulation time 188078817 ps
CPU time 1.3 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:46 PM PDT 24
Peak memory 196992 kb
Host smart-9179fc55-f486-4db3-b24b-4af3d1a8589f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90451110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.90451110
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1627859773
Short name T453
Test name
Test status
Simulation time 149155710 ps
CPU time 1.6 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:47 PM PDT 24
Peak memory 198444 kb
Host smart-d8f86a6a-f669-4f16-b190-ef2a26aaa866
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627859773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1627859773
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2194719941
Short name T675
Test name
Test status
Simulation time 103128810 ps
CPU time 1.9 seconds
Started Jul 31 04:36:44 PM PDT 24
Finished Jul 31 04:36:46 PM PDT 24
Peak memory 196188 kb
Host smart-2aba956d-cd46-43c6-80af-f005adf284db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194719941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2194719941
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2063702302
Short name T15
Test name
Test status
Simulation time 52131286 ps
CPU time 1.04 seconds
Started Jul 31 04:36:44 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 196392 kb
Host smart-48f5fa11-c2ef-43e4-aab2-6b413d7d797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063702302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2063702302
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1779443741
Short name T689
Test name
Test status
Simulation time 131641223 ps
CPU time 1.04 seconds
Started Jul 31 04:36:44 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 196540 kb
Host smart-4df6d5e4-3a57-4741-9dcd-9db23f702777
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779443741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1779443741
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3114005890
Short name T181
Test name
Test status
Simulation time 76060396 ps
CPU time 3.18 seconds
Started Jul 31 04:36:46 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 198404 kb
Host smart-279facb5-4d1c-4096-a019-073740dcea3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114005890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3114005890
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4174114210
Short name T349
Test name
Test status
Simulation time 57377500 ps
CPU time 1 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:47 PM PDT 24
Peak memory 195940 kb
Host smart-3ac8e770-0beb-484b-9a82-1db45778209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174114210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4174114210
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2200223802
Short name T26
Test name
Test status
Simulation time 273474850 ps
CPU time 1.12 seconds
Started Jul 31 04:36:44 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 195868 kb
Host smart-f816287d-4c9e-4dbf-9ae0-00ef523d7237
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200223802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2200223802
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3561753142
Short name T607
Test name
Test status
Simulation time 13533064863 ps
CPU time 157.01 seconds
Started Jul 31 04:36:46 PM PDT 24
Finished Jul 31 04:39:23 PM PDT 24
Peak memory 198516 kb
Host smart-541d7096-692d-4dd8-a504-85307048603d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561753142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3561753142
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2769147382
Short name T686
Test name
Test status
Simulation time 113662706770 ps
CPU time 280.51 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:41:24 PM PDT 24
Peak memory 198768 kb
Host smart-54bf4940-4f69-4573-907e-d3a573c37de3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2769147382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2769147382
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1832542798
Short name T163
Test name
Test status
Simulation time 17708817 ps
CPU time 0.56 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:36:43 PM PDT 24
Peak memory 195028 kb
Host smart-a5a8041e-975c-402a-866a-b47c9a3a4c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832542798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1832542798
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3094614769
Short name T363
Test name
Test status
Simulation time 19642277 ps
CPU time 0.68 seconds
Started Jul 31 04:36:42 PM PDT 24
Finished Jul 31 04:36:43 PM PDT 24
Peak memory 196272 kb
Host smart-2f5a7dd0-d58c-4dda-84cb-262423ab4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094614769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3094614769
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2251412975
Short name T210
Test name
Test status
Simulation time 1537142757 ps
CPU time 12.31 seconds
Started Jul 31 04:36:41 PM PDT 24
Finished Jul 31 04:36:54 PM PDT 24
Peak memory 197380 kb
Host smart-e275f8c7-0058-47f4-8f19-e82319cdc6e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251412975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2251412975
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1361007009
Short name T21
Test name
Test status
Simulation time 66584844 ps
CPU time 0.74 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 196220 kb
Host smart-a819d57f-1ea3-45be-af51-67e1a2ca3890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361007009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1361007009
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.4260534617
Short name T421
Test name
Test status
Simulation time 180802112 ps
CPU time 1.28 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 197620 kb
Host smart-85c471a9-3c18-4843-b297-02c1e6da52b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260534617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.4260534617
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1021164342
Short name T192
Test name
Test status
Simulation time 71924440 ps
CPU time 2.78 seconds
Started Jul 31 04:36:42 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 198360 kb
Host smart-ea9a1109-13e9-4666-a1fe-bee92c670131
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021164342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1021164342
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1650414312
Short name T313
Test name
Test status
Simulation time 544068079 ps
CPU time 2.77 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:48 PM PDT 24
Peak memory 196260 kb
Host smart-f9028b2d-4f7e-46a2-aa94-a7583eb43303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650414312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1650414312
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2438992338
Short name T328
Test name
Test status
Simulation time 80945766 ps
CPU time 0.67 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 194860 kb
Host smart-21d1f4f5-0d3e-4030-be24-7cd691ca0d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438992338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2438992338
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3468201700
Short name T507
Test name
Test status
Simulation time 24350380 ps
CPU time 0.83 seconds
Started Jul 31 04:36:43 PM PDT 24
Finished Jul 31 04:36:44 PM PDT 24
Peak memory 196196 kb
Host smart-56196df6-2258-4531-aa3b-23712db30421
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468201700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3468201700
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.188535811
Short name T443
Test name
Test status
Simulation time 310569037 ps
CPU time 2.76 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:36:50 PM PDT 24
Peak memory 198320 kb
Host smart-99a398f1-8d7e-45b4-90f4-3fbb1e5dfe62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188535811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.188535811
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3405265265
Short name T542
Test name
Test status
Simulation time 22781440 ps
CPU time 0.87 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:46 PM PDT 24
Peak memory 196864 kb
Host smart-b5ab8d50-a0bb-4e1f-a4b7-dc1340cd5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405265265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3405265265
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2864797711
Short name T75
Test name
Test status
Simulation time 78246102 ps
CPU time 0.76 seconds
Started Jul 31 04:36:44 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 196352 kb
Host smart-88febfc8-7ba4-48d2-9642-19670107b602
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864797711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2864797711
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3889174442
Short name T326
Test name
Test status
Simulation time 11985655036 ps
CPU time 171.92 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:39:37 PM PDT 24
Peak memory 198556 kb
Host smart-b59a7ce6-ad70-4f56-87c0-f171e3e81b61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889174442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3889174442
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3411611479
Short name T494
Test name
Test status
Simulation time 28299177 ps
CPU time 0.57 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 194212 kb
Host smart-b782370b-5a4c-4b76-9d7d-e038a2193f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411611479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3411611479
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.4052967627
Short name T201
Test name
Test status
Simulation time 158746495 ps
CPU time 0.65 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:36:48 PM PDT 24
Peak memory 194328 kb
Host smart-86237726-5d51-48e7-80a3-3716ad41085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052967627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.4052967627
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2077038417
Short name T143
Test name
Test status
Simulation time 395796539 ps
CPU time 10.76 seconds
Started Jul 31 04:36:49 PM PDT 24
Finished Jul 31 04:37:00 PM PDT 24
Peak memory 198516 kb
Host smart-55595fc6-b2c9-453f-8aab-5d96e0594ff3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077038417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2077038417
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1924945946
Short name T665
Test name
Test status
Simulation time 1383103094 ps
CPU time 0.91 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 197356 kb
Host smart-e787f893-0232-4077-9fbb-454cfdb2712e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924945946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1924945946
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1340914489
Short name T550
Test name
Test status
Simulation time 64963852 ps
CPU time 0.72 seconds
Started Jul 31 04:36:46 PM PDT 24
Finished Jul 31 04:36:47 PM PDT 24
Peak memory 195652 kb
Host smart-b415500b-8636-4e3e-8a9e-10809e8fbf89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340914489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1340914489
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3338508840
Short name T254
Test name
Test status
Simulation time 36215995 ps
CPU time 1.54 seconds
Started Jul 31 04:36:48 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 198528 kb
Host smart-92319468-1774-4a3b-963e-3d03696ff47c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338508840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3338508840
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.304968363
Short name T655
Test name
Test status
Simulation time 528719755 ps
CPU time 2.41 seconds
Started Jul 31 04:36:50 PM PDT 24
Finished Jul 31 04:36:53 PM PDT 24
Peak memory 197640 kb
Host smart-323ab938-eb55-4182-9914-fc8dde4d641d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304968363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.304968363
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.704724674
Short name T145
Test name
Test status
Simulation time 58029079 ps
CPU time 1.13 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:46 PM PDT 24
Peak memory 197456 kb
Host smart-c44d9237-1755-464d-af05-ce5f20e8fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704724674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.704724674
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2702843816
Short name T138
Test name
Test status
Simulation time 114576025 ps
CPU time 1.2 seconds
Started Jul 31 04:36:44 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 198388 kb
Host smart-46ecfe1f-37fb-4d37-b23b-5003131dd3ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702843816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2702843816
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.319458104
Short name T397
Test name
Test status
Simulation time 551636332 ps
CPU time 6.09 seconds
Started Jul 31 04:36:49 PM PDT 24
Finished Jul 31 04:36:56 PM PDT 24
Peak memory 198428 kb
Host smart-6d8e625d-64e5-477b-9c1d-949b9ebac402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319458104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.319458104
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1587897184
Short name T489
Test name
Test status
Simulation time 28942916 ps
CPU time 0.88 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:36:48 PM PDT 24
Peak memory 196664 kb
Host smart-2a23285a-1266-4052-8253-810c5b25a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587897184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1587897184
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1368352279
Short name T713
Test name
Test status
Simulation time 59181416 ps
CPU time 0.89 seconds
Started Jul 31 04:36:45 PM PDT 24
Finished Jul 31 04:36:45 PM PDT 24
Peak memory 196864 kb
Host smart-a35a64f1-13de-4354-863a-601ba4ec7d7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368352279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1368352279
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3323083732
Short name T77
Test name
Test status
Simulation time 24510467370 ps
CPU time 173.68 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 04:39:41 PM PDT 24
Peak memory 198572 kb
Host smart-c6727e79-b85b-41a4-99e0-753d89e856b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323083732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3323083732
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.973687172
Short name T58
Test name
Test status
Simulation time 191994571646 ps
CPU time 1839.07 seconds
Started Jul 31 04:36:47 PM PDT 24
Finished Jul 31 05:07:26 PM PDT 24
Peak memory 198696 kb
Host smart-914a54a7-54fc-4e00-967b-94bb01878f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=973687172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.973687172
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3942306035
Short name T886
Test name
Test status
Simulation time 290077351 ps
CPU time 1.03 seconds
Started Jul 31 04:22:45 PM PDT 24
Finished Jul 31 04:22:46 PM PDT 24
Peak memory 195472 kb
Host smart-b91877cb-5cd8-48e1-982e-b0a643cd432b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3942306035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3942306035
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3991611545
Short name T891
Test name
Test status
Simulation time 66983057 ps
CPU time 1.03 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 197780 kb
Host smart-bce01aa5-7f0e-48f3-9eb1-9fb802e76331
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991611545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3991611545
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2371918502
Short name T909
Test name
Test status
Simulation time 337717468 ps
CPU time 1.28 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 196548 kb
Host smart-52185303-eb4a-4643-bfa1-e7fc14a2e10a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2371918502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2371918502
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1362343456
Short name T931
Test name
Test status
Simulation time 174951087 ps
CPU time 0.9 seconds
Started Jul 31 04:23:54 PM PDT 24
Finished Jul 31 04:23:55 PM PDT 24
Peak memory 196376 kb
Host smart-5ca91f60-61a6-4d3d-ac66-40968d977a36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362343456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1362343456
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1019184866
Short name T910
Test name
Test status
Simulation time 253096835 ps
CPU time 1.2 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 196304 kb
Host smart-8f8bb6b2-511e-4e1b-9847-8d3c65d6dd4c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1019184866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1019184866
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1463176704
Short name T877
Test name
Test status
Simulation time 55537452 ps
CPU time 0.94 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 196048 kb
Host smart-a0b39cb8-4b6f-491c-885c-11af05b09bfe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463176704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1463176704
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2893613055
Short name T855
Test name
Test status
Simulation time 89711056 ps
CPU time 1.24 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:32 PM PDT 24
Peak memory 195128 kb
Host smart-50a3d132-59a2-4189-8776-057570ad7473
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2893613055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2893613055
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3797691900
Short name T854
Test name
Test status
Simulation time 38501132 ps
CPU time 1.11 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 194220 kb
Host smart-e59a54f7-f9dd-4541-82dd-d505d52a499f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797691900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3797691900
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1116172618
Short name T850
Test name
Test status
Simulation time 41284372 ps
CPU time 0.9 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:20:42 PM PDT 24
Peak memory 196184 kb
Host smart-fc706c56-94eb-4574-a25d-d2a7baba8048
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1116172618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1116172618
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2975261051
Short name T940
Test name
Test status
Simulation time 50045661 ps
CPU time 1.02 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:23:49 PM PDT 24
Peak memory 197672 kb
Host smart-78b5f40f-1e23-41d3-b86a-7a93c445e279
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975261051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2975261051
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2483262192
Short name T887
Test name
Test status
Simulation time 50225780 ps
CPU time 1.13 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 196436 kb
Host smart-b31806ec-41a3-4e37-8e9c-aa823483d5ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2483262192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2483262192
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2429823152
Short name T936
Test name
Test status
Simulation time 134043806 ps
CPU time 1.08 seconds
Started Jul 31 04:23:11 PM PDT 24
Finished Jul 31 04:23:12 PM PDT 24
Peak memory 198212 kb
Host smart-02462e05-23bc-43d3-8a15-22cac5947afb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429823152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2429823152
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.180493852
Short name T937
Test name
Test status
Simulation time 109207526 ps
CPU time 1.26 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 195160 kb
Host smart-dfd72240-80fc-4042-9f34-a9d5e9789cd5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=180493852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.180493852
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2394946423
Short name T935
Test name
Test status
Simulation time 174712155 ps
CPU time 0.94 seconds
Started Jul 31 04:23:23 PM PDT 24
Finished Jul 31 04:23:24 PM PDT 24
Peak memory 196344 kb
Host smart-c4bc7c45-66b5-451f-855d-4f2e1b95ae18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394946423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2394946423
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3811354147
Short name T930
Test name
Test status
Simulation time 63829414 ps
CPU time 1.14 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:23:48 PM PDT 24
Peak memory 196372 kb
Host smart-0149e2eb-bb3d-4e8f-91ed-ac30479269a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3811354147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3811354147
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3999067105
Short name T875
Test name
Test status
Simulation time 39099646 ps
CPU time 1.01 seconds
Started Jul 31 04:22:26 PM PDT 24
Finished Jul 31 04:22:27 PM PDT 24
Peak memory 197648 kb
Host smart-be207229-4765-4305-a6a6-b9adbaf05e39
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999067105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3999067105
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3483811308
Short name T917
Test name
Test status
Simulation time 126777856 ps
CPU time 0.96 seconds
Started Jul 31 04:25:23 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 195460 kb
Host smart-3666f5f1-9779-45c6-8fe2-99166ad50205
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3483811308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3483811308
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3492717138
Short name T912
Test name
Test status
Simulation time 88447821 ps
CPU time 0.88 seconds
Started Jul 31 04:21:10 PM PDT 24
Finished Jul 31 04:21:10 PM PDT 24
Peak memory 195752 kb
Host smart-a7ae10ca-1e9b-4208-9b3f-ea20c468936e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492717138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3492717138
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1584108953
Short name T941
Test name
Test status
Simulation time 179443107 ps
CPU time 1.06 seconds
Started Jul 31 04:21:33 PM PDT 24
Finished Jul 31 04:21:34 PM PDT 24
Peak memory 196312 kb
Host smart-03f65792-2961-448c-bf73-9ab33f8677c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1584108953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1584108953
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2494397200
Short name T865
Test name
Test status
Simulation time 193062496 ps
CPU time 0.92 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:23:49 PM PDT 24
Peak memory 197144 kb
Host smart-0f0a0cd0-ce18-43c1-9e29-c853a9eaeef9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494397200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2494397200
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3818449489
Short name T856
Test name
Test status
Simulation time 119818162 ps
CPU time 1.21 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:02 PM PDT 24
Peak memory 197600 kb
Host smart-e8748de9-810b-452d-8ef3-ec91cd2e314d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3818449489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3818449489
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2716646271
Short name T895
Test name
Test status
Simulation time 193118670 ps
CPU time 0.8 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 196392 kb
Host smart-8e0e5feb-339f-43e3-acf0-5b96532bf4d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716646271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2716646271
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.729601195
Short name T907
Test name
Test status
Simulation time 57823073 ps
CPU time 1 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:23:49 PM PDT 24
Peak memory 196308 kb
Host smart-e36a6ede-9830-47df-ba12-a417ac5fe995
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=729601195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.729601195
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.57309106
Short name T919
Test name
Test status
Simulation time 41563234 ps
CPU time 1.17 seconds
Started Jul 31 04:23:34 PM PDT 24
Finished Jul 31 04:23:35 PM PDT 24
Peak memory 195296 kb
Host smart-0ad3fa5d-89e8-473a-bca8-05d844fb3b38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57309106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.57309106
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1882981899
Short name T859
Test name
Test status
Simulation time 70138723 ps
CPU time 1.34 seconds
Started Jul 31 04:20:55 PM PDT 24
Finished Jul 31 04:20:56 PM PDT 24
Peak memory 196280 kb
Host smart-a16071eb-5d5d-440c-b654-9b736a8950a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1882981899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1882981899
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225733939
Short name T942
Test name
Test status
Simulation time 207165875 ps
CPU time 1.24 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:43 PM PDT 24
Peak memory 195332 kb
Host smart-ac617175-a50b-489b-9547-1d6adbb0191d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225733939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4225733939
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2655047849
Short name T872
Test name
Test status
Simulation time 311724068 ps
CPU time 1.3 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:33 PM PDT 24
Peak memory 195568 kb
Host smart-5f65e3d6-bfb0-489d-a08d-de98e9da2884
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2655047849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2655047849
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3282050117
Short name T848
Test name
Test status
Simulation time 172289432 ps
CPU time 1.21 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 197544 kb
Host smart-12b58fee-daeb-4234-892d-9bea349693ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282050117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3282050117
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.591748883
Short name T860
Test name
Test status
Simulation time 80014596 ps
CPU time 0.95 seconds
Started Jul 31 04:23:34 PM PDT 24
Finished Jul 31 04:23:35 PM PDT 24
Peak memory 194680 kb
Host smart-701c6164-73bf-4fb6-badc-6a5465de05a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=591748883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.591748883
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2525196965
Short name T934
Test name
Test status
Simulation time 86328886 ps
CPU time 1.32 seconds
Started Jul 31 04:22:16 PM PDT 24
Finished Jul 31 04:22:17 PM PDT 24
Peak memory 196660 kb
Host smart-72d26d18-620c-4d10-9f44-b13540ec41e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525196965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2525196965
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3984362268
Short name T902
Test name
Test status
Simulation time 47186988 ps
CPU time 0.98 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 195472 kb
Host smart-dbf3cb21-fdbe-446e-9e64-80249309bf0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3984362268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3984362268
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2853786493
Short name T924
Test name
Test status
Simulation time 161632442 ps
CPU time 1.07 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:23:49 PM PDT 24
Peak memory 196264 kb
Host smart-731464e6-c47d-402f-95d0-d719c9fc8f62
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853786493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2853786493
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1167930820
Short name T861
Test name
Test status
Simulation time 718157677 ps
CPU time 1.18 seconds
Started Jul 31 04:23:49 PM PDT 24
Finished Jul 31 04:23:50 PM PDT 24
Peak memory 196296 kb
Host smart-1cc89cb7-0616-47ad-872a-05d60f157b4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1167930820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1167930820
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1154922990
Short name T882
Test name
Test status
Simulation time 281076228 ps
CPU time 1.19 seconds
Started Jul 31 04:23:16 PM PDT 24
Finished Jul 31 04:23:18 PM PDT 24
Peak memory 195760 kb
Host smart-cda5e0be-955d-49e3-92a8-8252d2c5d45c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154922990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1154922990
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3255765695
Short name T862
Test name
Test status
Simulation time 69878111 ps
CPU time 0.94 seconds
Started Jul 31 04:23:49 PM PDT 24
Finished Jul 31 04:23:50 PM PDT 24
Peak memory 196300 kb
Host smart-e524574e-78af-4f85-9d88-da8c82734cfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3255765695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3255765695
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.97532448
Short name T923
Test name
Test status
Simulation time 51454172 ps
CPU time 0.97 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 195996 kb
Host smart-07977f52-adf5-4237-afeb-19bf5e8e95d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97532448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.97532448
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3563614207
Short name T921
Test name
Test status
Simulation time 414894446 ps
CPU time 1.03 seconds
Started Jul 31 04:30:30 PM PDT 24
Finished Jul 31 04:30:31 PM PDT 24
Peak memory 195672 kb
Host smart-4a00b49e-19a5-4c00-a7a6-f02fce21bfa9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3563614207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3563614207
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1807975693
Short name T896
Test name
Test status
Simulation time 153229249 ps
CPU time 1.43 seconds
Started Jul 31 04:30:11 PM PDT 24
Finished Jul 31 04:30:13 PM PDT 24
Peak memory 196536 kb
Host smart-17dbbfe5-8ca0-41c4-957a-b798da54010a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807975693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1807975693
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2140964368
Short name T897
Test name
Test status
Simulation time 270042453 ps
CPU time 0.91 seconds
Started Jul 31 04:30:08 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 195460 kb
Host smart-811af14a-c9d2-4596-bf84-401b50aee535
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2140964368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2140964368
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3293488130
Short name T938
Test name
Test status
Simulation time 79523345 ps
CPU time 1.25 seconds
Started Jul 31 04:30:25 PM PDT 24
Finished Jul 31 04:30:27 PM PDT 24
Peak memory 195924 kb
Host smart-255a1eda-db10-4d67-b8f5-a9b4babb7eb5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293488130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3293488130
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1131848479
Short name T883
Test name
Test status
Simulation time 52996484 ps
CPU time 1.34 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 196596 kb
Host smart-b62e4f73-064e-4a4c-b90a-ebcc04fb534b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1131848479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1131848479
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3088619419
Short name T933
Test name
Test status
Simulation time 77823472 ps
CPU time 0.91 seconds
Started Jul 31 04:30:08 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 196448 kb
Host smart-9162bd46-1dd9-4e75-8911-ed9de223eb94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088619419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3088619419
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.547480953
Short name T876
Test name
Test status
Simulation time 447743867 ps
CPU time 1.14 seconds
Started Jul 31 04:30:09 PM PDT 24
Finished Jul 31 04:30:10 PM PDT 24
Peak memory 196428 kb
Host smart-0e8ff29d-5188-44a1-9fdc-8a6b706baa7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=547480953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.547480953
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2284750271
Short name T898
Test name
Test status
Simulation time 47421330 ps
CPU time 0.87 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 195168 kb
Host smart-acdb9f1c-05d4-4a7d-9186-730d00a1d630
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284750271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2284750271
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.39224318
Short name T853
Test name
Test status
Simulation time 136910844 ps
CPU time 1.09 seconds
Started Jul 31 04:30:16 PM PDT 24
Finished Jul 31 04:30:18 PM PDT 24
Peak memory 197872 kb
Host smart-7e510cf0-5646-4809-be12-978c5471cb15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=39224318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.39224318
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4209773474
Short name T863
Test name
Test status
Simulation time 84639679 ps
CPU time 1.32 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 195520 kb
Host smart-8a7caed7-c42a-42f8-a530-81759bf458bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209773474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4209773474
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2367358938
Short name T858
Test name
Test status
Simulation time 45508959 ps
CPU time 0.89 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 194008 kb
Host smart-04124bee-5fa3-40a0-a472-0dfad1c492bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2367358938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2367358938
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1989883498
Short name T932
Test name
Test status
Simulation time 218669219 ps
CPU time 1.12 seconds
Started Jul 31 04:23:53 PM PDT 24
Finished Jul 31 04:23:54 PM PDT 24
Peak memory 197804 kb
Host smart-c6df55cd-2ee0-441c-a4a6-f6593968ffc0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989883498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1989883498
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.607515317
Short name T929
Test name
Test status
Simulation time 40469819 ps
CPU time 0.81 seconds
Started Jul 31 04:30:23 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 195328 kb
Host smart-0936a160-57e5-4ba6-b546-34eae7ba8661
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=607515317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.607515317
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193079236
Short name T900
Test name
Test status
Simulation time 276714344 ps
CPU time 1.2 seconds
Started Jul 31 04:30:08 PM PDT 24
Finished Jul 31 04:30:10 PM PDT 24
Peak memory 197936 kb
Host smart-09230816-bbbf-460a-828a-3385fbb0f88a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193079236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3193079236
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.856342481
Short name T915
Test name
Test status
Simulation time 88155045 ps
CPU time 1.31 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 196680 kb
Host smart-6149c6f9-a08d-49f6-b0c3-7d870c6c1797
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=856342481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.856342481
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3427146978
Short name T843
Test name
Test status
Simulation time 48693707 ps
CPU time 1.21 seconds
Started Jul 31 04:30:10 PM PDT 24
Finished Jul 31 04:30:11 PM PDT 24
Peak memory 195476 kb
Host smart-6803cedd-2223-461a-93b1-4ff14353d900
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427146978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3427146978
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3966288609
Short name T925
Test name
Test status
Simulation time 56649981 ps
CPU time 1.14 seconds
Started Jul 31 04:30:08 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 197880 kb
Host smart-eab58231-9279-4bb5-834d-8c13237f8a08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3966288609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3966288609
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3891394968
Short name T881
Test name
Test status
Simulation time 273993636 ps
CPU time 1.11 seconds
Started Jul 31 04:30:11 PM PDT 24
Finished Jul 31 04:30:12 PM PDT 24
Peak memory 197824 kb
Host smart-241558b1-e94e-45fd-a402-58c9ea5b4a61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891394968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3891394968
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.647492039
Short name T926
Test name
Test status
Simulation time 141314872 ps
CPU time 1.07 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 197900 kb
Host smart-30dd924c-0f11-4def-84f8-6901e11fa614
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=647492039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.647492039
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3540401433
Short name T849
Test name
Test status
Simulation time 148016119 ps
CPU time 1.19 seconds
Started Jul 31 04:30:08 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 196392 kb
Host smart-25a88acf-fc8b-4fa5-9fc9-9f7b549d3534
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540401433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3540401433
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2396711915
Short name T890
Test name
Test status
Simulation time 26125170 ps
CPU time 0.89 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:07 PM PDT 24
Peak memory 196328 kb
Host smart-e3bfa862-ec0f-40b8-b948-d8a5517204fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2396711915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2396711915
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929676785
Short name T871
Test name
Test status
Simulation time 186879847 ps
CPU time 0.99 seconds
Started Jul 31 04:30:07 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 195656 kb
Host smart-0330368f-79b4-45a4-9299-6206cf9830f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929676785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.929676785
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2530433107
Short name T908
Test name
Test status
Simulation time 280139995 ps
CPU time 1.28 seconds
Started Jul 31 04:30:14 PM PDT 24
Finished Jul 31 04:30:15 PM PDT 24
Peak memory 196516 kb
Host smart-fdb21fa7-e0c0-4060-bc59-424e369c6d90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2530433107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2530433107
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.286380479
Short name T844
Test name
Test status
Simulation time 41720668 ps
CPU time 1.02 seconds
Started Jul 31 04:30:19 PM PDT 24
Finished Jul 31 04:30:20 PM PDT 24
Peak memory 195784 kb
Host smart-ef106817-6cf6-479e-bff7-9cd94a57d8d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286380479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.286380479
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3570945657
Short name T880
Test name
Test status
Simulation time 39340835 ps
CPU time 1.02 seconds
Started Jul 31 04:30:14 PM PDT 24
Finished Jul 31 04:30:15 PM PDT 24
Peak memory 195536 kb
Host smart-8c07e532-da0c-4bab-bee1-879e2610ca08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3570945657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3570945657
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3375073008
Short name T878
Test name
Test status
Simulation time 102823038 ps
CPU time 1.34 seconds
Started Jul 31 04:30:22 PM PDT 24
Finished Jul 31 04:30:23 PM PDT 24
Peak memory 196576 kb
Host smart-0cc26d2e-a2fe-44a3-acab-0ac5b4deaf88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375073008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3375073008
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.157872212
Short name T913
Test name
Test status
Simulation time 54581493 ps
CPU time 0.85 seconds
Started Jul 31 04:30:12 PM PDT 24
Finished Jul 31 04:30:13 PM PDT 24
Peak memory 197636 kb
Host smart-bd0d7905-9657-49bf-bd98-95d3cbcb5827
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=157872212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.157872212
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.171057779
Short name T911
Test name
Test status
Simulation time 112982160 ps
CPU time 1.06 seconds
Started Jul 31 04:30:15 PM PDT 24
Finished Jul 31 04:30:16 PM PDT 24
Peak memory 195820 kb
Host smart-8e368263-39b5-4147-a4b5-96ffdc44c844
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171057779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.171057779
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.854059870
Short name T928
Test name
Test status
Simulation time 28223601 ps
CPU time 0.78 seconds
Started Jul 31 04:30:13 PM PDT 24
Finished Jul 31 04:30:14 PM PDT 24
Peak memory 195836 kb
Host smart-325515bd-770c-4634-a35d-7ca59f03725b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=854059870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.854059870
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.468908818
Short name T888
Test name
Test status
Simulation time 565365878 ps
CPU time 1.06 seconds
Started Jul 31 04:30:14 PM PDT 24
Finished Jul 31 04:30:15 PM PDT 24
Peak memory 196568 kb
Host smart-412226ff-cce2-46e3-a1cf-8b2dcc484641
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468908818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.468908818
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1361798617
Short name T846
Test name
Test status
Simulation time 270047828 ps
CPU time 1.12 seconds
Started Jul 31 04:30:15 PM PDT 24
Finished Jul 31 04:30:17 PM PDT 24
Peak memory 195712 kb
Host smart-8db13bab-e602-4080-8816-41d4790edb96
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1361798617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1361798617
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2032512092
Short name T922
Test name
Test status
Simulation time 25276926 ps
CPU time 0.85 seconds
Started Jul 31 04:30:17 PM PDT 24
Finished Jul 31 04:30:19 PM PDT 24
Peak memory 195252 kb
Host smart-c783d0f5-b804-4210-85c0-b1b5c8b5819b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032512092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2032512092
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2926881468
Short name T899
Test name
Test status
Simulation time 271346587 ps
CPU time 1.51 seconds
Started Jul 31 04:23:55 PM PDT 24
Finished Jul 31 04:23:56 PM PDT 24
Peak memory 196532 kb
Host smart-a08a18d6-22ca-4374-ac28-6ab3f333c1ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2926881468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2926881468
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.11394507
Short name T873
Test name
Test status
Simulation time 41712088 ps
CPU time 1.04 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 196468 kb
Host smart-f23bd083-68f6-40e1-a6ca-54b047e641d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11394507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.11394507
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2814314781
Short name T869
Test name
Test status
Simulation time 43639242 ps
CPU time 1.18 seconds
Started Jul 31 04:30:17 PM PDT 24
Finished Jul 31 04:30:19 PM PDT 24
Peak memory 195796 kb
Host smart-3b093a11-e3ed-4d78-98fe-5382bde4f52b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2814314781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2814314781
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2164617192
Short name T885
Test name
Test status
Simulation time 237563663 ps
CPU time 1.02 seconds
Started Jul 31 04:30:17 PM PDT 24
Finished Jul 31 04:30:19 PM PDT 24
Peak memory 196316 kb
Host smart-49f5abe2-609d-478f-8a79-40c86c39989c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164617192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2164617192
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.544444454
Short name T868
Test name
Test status
Simulation time 129320153 ps
CPU time 1.09 seconds
Started Jul 31 04:30:27 PM PDT 24
Finished Jul 31 04:30:28 PM PDT 24
Peak memory 195616 kb
Host smart-4b9d4569-c85d-4582-9f2b-a6607d1a3f18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=544444454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.544444454
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.655138046
Short name T905
Test name
Test status
Simulation time 296038833 ps
CPU time 1.11 seconds
Started Jul 31 04:30:18 PM PDT 24
Finished Jul 31 04:30:20 PM PDT 24
Peak memory 196340 kb
Host smart-074ea6db-819e-46cd-8f80-d1ef185181b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655138046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.655138046
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.292214285
Short name T870
Test name
Test status
Simulation time 149467003 ps
CPU time 1.11 seconds
Started Jul 31 04:30:13 PM PDT 24
Finished Jul 31 04:30:14 PM PDT 24
Peak memory 195516 kb
Host smart-8e62634a-aa58-452c-8be9-2f5e7b70c2e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=292214285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.292214285
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2862285321
Short name T867
Test name
Test status
Simulation time 61925236 ps
CPU time 0.88 seconds
Started Jul 31 04:30:12 PM PDT 24
Finished Jul 31 04:30:13 PM PDT 24
Peak memory 195104 kb
Host smart-47ee79a7-a386-48e0-b378-b507c9882362
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862285321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2862285321
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3287736255
Short name T866
Test name
Test status
Simulation time 219933421 ps
CPU time 1.27 seconds
Started Jul 31 04:30:13 PM PDT 24
Finished Jul 31 04:30:14 PM PDT 24
Peak memory 197940 kb
Host smart-d6185e32-393a-4d0f-8af1-c58106aa87bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3287736255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3287736255
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2961831194
Short name T914
Test name
Test status
Simulation time 38101445 ps
CPU time 0.69 seconds
Started Jul 31 04:30:25 PM PDT 24
Finished Jul 31 04:30:26 PM PDT 24
Peak memory 194180 kb
Host smart-7506ad64-4aaa-43d4-a553-a260174bbdab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961831194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2961831194
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3608975148
Short name T906
Test name
Test status
Simulation time 63881498 ps
CPU time 1.07 seconds
Started Jul 31 04:30:19 PM PDT 24
Finished Jul 31 04:30:20 PM PDT 24
Peak memory 196432 kb
Host smart-3f756beb-a6bf-43c5-af05-3b15f596a208
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3608975148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3608975148
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.434856008
Short name T851
Test name
Test status
Simulation time 124730780 ps
CPU time 1.17 seconds
Started Jul 31 04:30:19 PM PDT 24
Finished Jul 31 04:30:20 PM PDT 24
Peak memory 196316 kb
Host smart-c25e2215-243c-4e76-af18-97158f2a83a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434856008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.434856008
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1137943802
Short name T894
Test name
Test status
Simulation time 331246316 ps
CPU time 1.17 seconds
Started Jul 31 04:30:23 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 197776 kb
Host smart-8b995ab9-ee11-46a3-b92d-974b8662d016
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1137943802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1137943802
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2123079240
Short name T884
Test name
Test status
Simulation time 51506681 ps
CPU time 1.39 seconds
Started Jul 31 04:30:23 PM PDT 24
Finished Jul 31 04:30:25 PM PDT 24
Peak memory 196720 kb
Host smart-fb9637b4-ede1-46aa-b41c-00c371e67a50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123079240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2123079240
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3472801039
Short name T920
Test name
Test status
Simulation time 55119722 ps
CPU time 0.95 seconds
Started Jul 31 04:30:21 PM PDT 24
Finished Jul 31 04:30:22 PM PDT 24
Peak memory 197668 kb
Host smart-2be3f440-032b-437e-a4ea-b792ab5c926f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3472801039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3472801039
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2323401879
Short name T904
Test name
Test status
Simulation time 101580095 ps
CPU time 0.93 seconds
Started Jul 31 04:30:23 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 197256 kb
Host smart-b9eb0294-129c-47c8-87fc-0dd4219ae436
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323401879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2323401879
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2616695153
Short name T916
Test name
Test status
Simulation time 147343688 ps
CPU time 1.11 seconds
Started Jul 31 04:30:19 PM PDT 24
Finished Jul 31 04:30:20 PM PDT 24
Peak memory 197960 kb
Host smart-08f1e090-0821-447e-9b56-cab62e858736
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2616695153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2616695153
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1730630062
Short name T901
Test name
Test status
Simulation time 138491453 ps
CPU time 1.21 seconds
Started Jul 31 04:30:18 PM PDT 24
Finished Jul 31 04:30:20 PM PDT 24
Peak memory 197936 kb
Host smart-d1265050-923a-4737-9c1f-642643083bbf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730630062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1730630062
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3416364245
Short name T864
Test name
Test status
Simulation time 51859138 ps
CPU time 1.39 seconds
Started Jul 31 04:30:20 PM PDT 24
Finished Jul 31 04:30:21 PM PDT 24
Peak memory 197924 kb
Host smart-9fa5b652-d722-4234-a383-7487d5cfca26
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3416364245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3416364245
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1280762669
Short name T847
Test name
Test status
Simulation time 51783890 ps
CPU time 1.16 seconds
Started Jul 31 04:30:23 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 196248 kb
Host smart-f2b816c5-208b-45c7-9603-5f4766b54d36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280762669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1280762669
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.978154486
Short name T939
Test name
Test status
Simulation time 181387809 ps
CPU time 1.24 seconds
Started Jul 31 04:30:23 PM PDT 24
Finished Jul 31 04:30:25 PM PDT 24
Peak memory 197912 kb
Host smart-e946b8eb-a596-4acc-916c-303b4a1885e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=978154486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.978154486
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.527814554
Short name T889
Test name
Test status
Simulation time 91927333 ps
CPU time 1.24 seconds
Started Jul 31 04:30:22 PM PDT 24
Finished Jul 31 04:30:23 PM PDT 24
Peak memory 196428 kb
Host smart-cd4193d4-2b36-489e-8283-5b9063d5de88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527814554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.527814554
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2321275956
Short name T845
Test name
Test status
Simulation time 212327590 ps
CPU time 1.16 seconds
Started Jul 31 04:20:47 PM PDT 24
Finished Jul 31 04:20:49 PM PDT 24
Peak memory 196328 kb
Host smart-1553dab9-58d2-4dbd-b2c6-6c7af5c39902
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2321275956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2321275956
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1880486501
Short name T879
Test name
Test status
Simulation time 70859851 ps
CPU time 1.27 seconds
Started Jul 31 04:25:25 PM PDT 24
Finished Jul 31 04:25:27 PM PDT 24
Peak memory 195088 kb
Host smart-4169a159-5bce-4dc7-984f-fe34cdef3818
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880486501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1880486501
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1803632377
Short name T918
Test name
Test status
Simulation time 544562442 ps
CPU time 1.38 seconds
Started Jul 31 04:22:00 PM PDT 24
Finished Jul 31 04:22:01 PM PDT 24
Peak memory 196224 kb
Host smart-e04a134b-9935-4099-aca4-01c9c53cea0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1803632377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1803632377
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151986942
Short name T892
Test name
Test status
Simulation time 56447380 ps
CPU time 1.21 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 194816 kb
Host smart-7c7b4544-5d31-4770-8c4d-389c61391bcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151986942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1151986942
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3375393830
Short name T927
Test name
Test status
Simulation time 230765888 ps
CPU time 1.26 seconds
Started Jul 31 04:21:48 PM PDT 24
Finished Jul 31 04:21:49 PM PDT 24
Peak memory 196360 kb
Host smart-ffbb78ac-ff51-4f8f-b951-be46315ea450
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3375393830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3375393830
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1526852196
Short name T874
Test name
Test status
Simulation time 51594616 ps
CPU time 1.32 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 195232 kb
Host smart-f227bc50-2ad0-4a2f-9e3f-598082fbedda
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526852196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1526852196
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2936783983
Short name T893
Test name
Test status
Simulation time 51436295 ps
CPU time 0.99 seconds
Started Jul 31 04:23:45 PM PDT 24
Finished Jul 31 04:23:46 PM PDT 24
Peak memory 195468 kb
Host smart-fe2f19cf-49af-4c44-aca8-80fb1ca414c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2936783983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2936783983
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3482866429
Short name T903
Test name
Test status
Simulation time 103855530 ps
CPU time 0.85 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:32 PM PDT 24
Peak memory 193656 kb
Host smart-549d10de-b413-4124-93eb-53b48833dc55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482866429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3482866429
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2333234422
Short name T852
Test name
Test status
Simulation time 335116160 ps
CPU time 1.41 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 197608 kb
Host smart-1f4f811e-5563-4166-98fd-9592cfebc89f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2333234422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2333234422
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4256213781
Short name T857
Test name
Test status
Simulation time 173558078 ps
CPU time 0.95 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:20:42 PM PDT 24
Peak memory 196496 kb
Host smart-9a704593-65d7-45fe-a021-92e81b50cd40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256213781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4256213781
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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