Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2843306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12283680

1

T21

207

T22

633

T23

52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6147762	1			T21	125		T22	365		T23	30
values[0x0]	4421030	1			T21	68		T22	221		T23	16
values[0x1]	4558194	1			T21	75		T22	222		T23	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2199000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12927986

1

T21

220

T22

671

T23

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52880	1			T29	231		T109	2		T114	7
valid_sources[0x01]	64099	1			T27	4		T29	211		T109	1
valid_sources[0x02]	53321	1			T23	1		T24	10		T29	272
valid_sources[0x03]	51001	1			T24	4		T29	269		T109	3
valid_sources[0x04]	55587	1			T21	268		T27	3		T29	269
valid_sources[0x05]	67299	1			T29	275		T109	3		T47	3
valid_sources[0x06]	56816	1			T22	48		T24	7		T27	1
valid_sources[0x07]	54533	1			T29	324		T109	2		T47	1
valid_sources[0x08]	56884	1			T29	318		T114	11		T115	330
valid_sources[0x09]	54626	1			T29	298		T109	6		T114	8
valid_sources[0x0a]	56330	1			T29	257		T30	55		T114	12
valid_sources[0x0b]	55311	1			T29	293		T109	1		T114	3
valid_sources[0x0c]	56254	1			T24	8		T29	382		T109	4
valid_sources[0x0d]	146648	1			T22	45		T27	3		T29	240
valid_sources[0x0e]	55571	1			T27	4		T29	202		T109	1
valid_sources[0x0f]	56211	1			T29	316		T114	10		T115	318
valid_sources[0x10]	62592	1			T27	3		T29	292		T114	4
valid_sources[0x11]	51771	1			T29	300		T109	3		T114	6
valid_sources[0x12]	55672	1			T26	16		T27	5		T29	234
valid_sources[0x13]	55135	1			T29	282		T109	6		T47	2
valid_sources[0x14]	65973	1			T24	13		T27	3		T29	271
valid_sources[0x15]	57756	1			T29	289		T109	1		T114	8
valid_sources[0x16]	55877	1			T29	242		T109	1		T114	5
valid_sources[0x17]	53766	1			T27	4		T29	282		T109	2
valid_sources[0x18]	56708	1			T24	5		T29	244		T114	3
valid_sources[0x19]	63656	1			T24	15		T29	265		T114	4
valid_sources[0x1a]	58797	1			T29	231		T47	8		T114	3
valid_sources[0x1b]	51653	1			T27	1		T29	231		T47	3
valid_sources[0x1c]	59833	1			T23	3		T24	13		T29	274
valid_sources[0x1d]	56602	1			T24	7		T27	2		T29	291
valid_sources[0x1e]	51701	1			T24	10		T29	362		T109	4
valid_sources[0x1f]	56145	1			T26	20		T27	2		T29	300
valid_sources[0x20]	62315	1			T22	2		T27	1		T29	186
valid_sources[0x21]	55877	1			T29	276		T109	5		T47	3
valid_sources[0x22]	58309	1			T29	293		T114	4		T115	308
valid_sources[0x23]	54562	1			T23	1		T27	2		T29	279
valid_sources[0x24]	56710	1			T27	6		T29	229		T109	1
valid_sources[0x25]	62279	1			T29	342		T109	4		T114	12
valid_sources[0x26]	53737	1			T27	1		T29	271		T114	4
valid_sources[0x27]	54781	1			T27	2		T29	219		T109	3
valid_sources[0x28]	52323	1			T27	3		T29	196		T114	5
valid_sources[0x29]	114308	1			T29	236		T109	3		T114	5
valid_sources[0x2a]	53002	1			T23	1		T29	226		T109	1
valid_sources[0x2b]	51174	1			T24	9		T27	2		T29	272
valid_sources[0x2c]	61512	1			T27	1		T29	267		T114	10
valid_sources[0x2d]	58689	1			T29	256		T109	1		T47	4
valid_sources[0x2e]	58747	1			T27	2		T29	265		T109	4
valid_sources[0x2f]	51766	1			T27	1		T29	255		T109	3
valid_sources[0x30]	55839	1			T29	199		T109	1		T114	5
valid_sources[0x31]	51494	1			T24	1		T27	6		T29	281
valid_sources[0x32]	57854	1			T24	2		T29	224		T109	6
valid_sources[0x33]	55545	1			T29	285		T109	3		T114	13
valid_sources[0x34]	61958	1			T24	1		T29	355		T109	2
valid_sources[0x35]	63490	1			T22	63		T24	16		T27	1
valid_sources[0x36]	50925	1			T29	217		T109	1		T47	2
valid_sources[0x37]	55318	1			T29	177		T30	6		T47	3
valid_sources[0x38]	54846	1			T23	4		T27	11		T29	248
valid_sources[0x39]	61358	1			T27	1		T29	226		T114	9
valid_sources[0x3a]	62977	1			T24	1		T29	286		T109	2
valid_sources[0x3b]	52687	1			T27	1		T29	276		T114	8
valid_sources[0x3c]	54203	1			T29	254		T109	4		T114	8
valid_sources[0x3d]	207686	1			T23	4		T29	299		T114	5
valid_sources[0x3e]	63538	1			T22	1		T24	11		T29	222
valid_sources[0x3f]	59158	1			T29	255		T109	4		T47	6
valid_sources[0x40]	55458	1			T24	5		T29	303		T47	1
valid_sources[0x41]	51641	1			T27	1		T29	336		T109	2
valid_sources[0x42]	55115	1			T27	1		T29	300		T114	6
valid_sources[0x43]	55551	1			T29	249		T114	9		T115	315
valid_sources[0x44]	58427	1			T23	1		T24	2		T27	6
valid_sources[0x45]	56003	1			T22	35		T29	218		T47	2
valid_sources[0x46]	55905	1			T29	285		T114	6		T115	312
valid_sources[0x47]	58770	1			T29	326		T109	9		T114	10
valid_sources[0x48]	158837	1			T24	2		T27	15		T29	316
valid_sources[0x49]	50760	1			T24	9		T27	6		T29	193
valid_sources[0x4a]	62082	1			T27	1		T29	228		T109	2
valid_sources[0x4b]	51807	1			T22	32		T27	2		T29	226
valid_sources[0x4c]	56586	1			T24	1		T29	226		T109	1
valid_sources[0x4d]	52144	1			T29	245		T109	3		T114	5
valid_sources[0x4e]	56079	1			T29	187		T109	1		T47	3
valid_sources[0x4f]	57006	1			T24	3		T29	276		T109	1
valid_sources[0x50]	59277	1			T24	11		T29	352		T114	5
valid_sources[0x51]	58965	1			T29	338		T109	5		T114	7
valid_sources[0x52]	60864	1			T27	1		T29	255		T109	4
valid_sources[0x53]	56777	1			T28	925		T29	233		T114	5
valid_sources[0x54]	55336	1			T24	1		T29	311		T114	8
valid_sources[0x55]	53261	1			T27	2		T29	361		T109	3
valid_sources[0x56]	56553	1			T27	3		T29	353		T47	1
valid_sources[0x57]	54048	1			T29	376		T109	2		T114	5
valid_sources[0x58]	50918	1			T24	9		T27	2		T29	251
valid_sources[0x59]	64517	1			T27	7		T29	304		T114	5
valid_sources[0x5a]	54040	1			T29	264		T114	15		T115	300
valid_sources[0x5b]	55879	1			T22	11		T27	2		T29	290
valid_sources[0x5c]	56142	1			T27	1		T29	228		T114	9
valid_sources[0x5d]	58324	1			T23	2		T29	252		T30	16
valid_sources[0x5e]	60622	1			T23	1		T24	2		T27	1
valid_sources[0x5f]	59409	1			T23	1		T24	5		T29	284
valid_sources[0x60]	53506	1			T27	1		T29	331		T109	5
valid_sources[0x61]	55453	1			T27	9		T29	213		T114	5
valid_sources[0x62]	58126	1			T27	3		T29	255		T109	4
valid_sources[0x63]	56558	1			T24	1		T29	303		T109	5
valid_sources[0x64]	52676	1			T24	14		T27	2		T29	248
valid_sources[0x65]	60855	1			T27	2		T29	162		T114	8
valid_sources[0x66]	50498	1			T24	2		T29	341		T109	3
valid_sources[0x67]	62114	1			T23	3		T27	1		T29	271
valid_sources[0x68]	53239	1			T23	2		T29	321		T109	2
valid_sources[0x69]	53937	1			T22	128		T29	282		T109	2
valid_sources[0x6a]	86308	1			T27	2		T29	398		T30	65
valid_sources[0x6b]	56309	1			T23	1		T29	248		T109	6
valid_sources[0x6c]	61929	1			T27	1		T29	297		T109	5
valid_sources[0x6d]	57767	1			T27	9		T29	192		T109	2
valid_sources[0x6e]	54312	1			T29	225		T114	7		T115	318
valid_sources[0x6f]	57175	1			T29	210		T109	3		T47	2
valid_sources[0x70]	57757	1			T24	12		T27	1		T29	293
valid_sources[0x71]	57507	1			T27	2		T29	159		T109	4
valid_sources[0x72]	54319	1			T24	2		T27	2		T29	285
valid_sources[0x73]	58486	1			T24	5		T29	257		T47	1
valid_sources[0x74]	55799	1			T22	20		T25	216		T29	183
valid_sources[0x75]	53165	1			T29	281		T109	5		T114	11
valid_sources[0x76]	55545	1			T27	2		T29	236		T114	8
valid_sources[0x77]	56067	1			T24	10		T27	2		T29	329
valid_sources[0x78]	57633	1			T29	233		T114	7		T115	282
valid_sources[0x79]	54481	1			T29	216		T114	5		T115	252
valid_sources[0x7a]	53463	1			T24	8		T29	222		T114	4
valid_sources[0x7b]	58773	1			T29	198		T30	19		T109	4
valid_sources[0x7c]	51735	1			T24	4		T27	2		T29	231
valid_sources[0x7d]	52220	1			T29	278		T109	6		T114	7
valid_sources[0x7e]	60339	1			T24	4		T27	2		T29	312
valid_sources[0x7f]	57608	1			T27	8		T29	234		T30	15
valid_sources[0x80]	53893	1			T27	4		T29	309		T114	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3468404

1

T21

64

T22

190

T23

20

values[0x0]

all_enables

biggest_size

4407176

1

T21

68

T22

221

T23

16

values[0x1]

all_enables

biggest_size

4408100

1

T21

75

T22

222

T23

16