Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117740732	0	0	0
ctrl_en_input_filter_rd_A	117740732	48710	0	0
intr_ctrl_en_falling_rd_A	117740732	48726	0	0
intr_ctrl_en_lvlhigh_rd_A	117740732	48484	0	0
intr_ctrl_en_lvllow_rd_A	117740732	49129	0	0
intr_ctrl_en_rising_rd_A	117740732	48152	0	0
intr_enable_rd_A	117740732	47950	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	48710	0	0
T1	41877	269	0	0
T2	0	1922	0	0
T3	0	1	0	0
T4	0	150	0	0
T5	0	35	0	0
T6	0	188	0	0
T7	0	66	0	0
T8	0	79	0	0
T9	0	3429	0	0
T10	0	164	0	0
T11	3114	0	0	0
T12	6251	0	0	0
T13	7717	0	0	0
T14	654364	0	0	0
T15	5119	0	0	0
T16	14503	0	0	0
T17	1267	0	0	0
T18	3303	0	0	0
T19	7627	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	48726	0	0
T1	41877	298	0	0
T2	0	2032	0	0
T3	0	2	0	0
T4	0	181	0	0
T5	0	27	0	0
T6	0	117	0	0
T7	0	139	0	0
T8	0	51	0	0
T9	0	3618	0	0
T10	0	136	0	0
T11	3114	0	0	0
T12	6251	0	0	0
T13	7717	0	0	0
T14	654364	0	0	0
T15	5119	0	0	0
T16	14503	0	0	0
T17	1267	0	0	0
T18	3303	0	0	0
T19	7627	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	48484	0	0
T1	41877	333	0	0
T2	0	1942	0	0
T3	0	4	0	0
T4	0	185	0	0
T5	0	25	0	0
T6	0	186	0	0
T7	0	103	0	0
T8	0	48	0	0
T9	0	3550	0	0
T10	0	178	0	0
T11	3114	0	0	0
T12	6251	0	0	0
T13	7717	0	0	0
T14	654364	0	0	0
T15	5119	0	0	0
T16	14503	0	0	0
T17	1267	0	0	0
T18	3303	0	0	0
T19	7627	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	49129	0	0
T1	41877	272	0	0
T2	0	2105	0	0
T3	0	12	0	0
T4	0	155	0	0
T5	0	7	0	0
T6	0	172	0	0
T7	0	126	0	0
T8	0	44	0	0
T9	0	3457	0	0
T10	0	235	0	0
T11	3114	0	0	0
T12	6251	0	0	0
T13	7717	0	0	0
T14	654364	0	0	0
T15	5119	0	0	0
T16	14503	0	0	0
T17	1267	0	0	0
T18	3303	0	0	0
T19	7627	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	48152	0	0
T1	41877	306	0	0
T2	0	2353	0	0
T4	0	204	0	0
T5	0	8	0	0
T6	0	177	0	0
T7	0	76	0	0
T8	0	53	0	0
T9	0	3541	0	0
T10	0	203	0	0
T11	3114	0	0	0
T12	6251	0	0	0
T13	7717	0	0	0
T14	654364	0	0	0
T15	5119	0	0	0
T16	14503	0	0	0
T17	1267	0	0	0
T18	3303	0	0	0
T19	7627	0	0	0
T20	0	169	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117740732	47950	0	0
T1	41877	295	0	0
T2	0	2126	0	0
T4	0	179	0	0
T5	0	43	0	0
T6	0	99	0	0
T7	0	69	0	0
T8	0	39	0	0
T9	0	3245	0	0
T10	0	217	0	0
T11	3114	0	0	0
T12	6251	0	0	0
T13	7717	0	0	0
T14	654364	0	0	0
T15	5119	0	0	0
T16	14503	0	0	0
T17	1267	0	0	0
T18	3303	0	0	0
T19	7627	0	0	0
T20	0	223	0	0