Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3740451	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16880887

1

T35

62

T36

55

T37

249

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8198959	1			T35	20		T36	19		T37	32
values[0x0]	6101755	1			T35	34		T36	27		T37	127
values[0x1]	6320624	1			T35	20		T36	19		T37	113

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2869424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

17751914

1

T35

64

T36

58

T37

254

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	78078	1			T38	16		T41	1		T42	4
valid_sources[0x01]	76553	1			T37	1		T38	7		T41	2
valid_sources[0x02]	74562	1			T37	2		T38	1		T41	1
valid_sources[0x03]	74882	1			T38	4		T39	20		T41	5
valid_sources[0x04]	80205	1			T37	4		T39	5		T41	3
valid_sources[0x05]	73712	1			T37	2		T39	7		T41	2
valid_sources[0x06]	77224	1			T37	2		T41	3		T43	1
valid_sources[0x07]	74341	1			T37	1		T38	15		T42	6
valid_sources[0x08]	78222	1			T38	1		T41	1		T42	7
valid_sources[0x09]	71566	1			T37	3		T38	4		T39	3
valid_sources[0x0a]	190075	1			T37	1		T38	10		T41	1
valid_sources[0x0b]	79557	1			T38	1		T39	5		T41	2
valid_sources[0x0c]	80622	1			T39	27		T42	8		T43	3
valid_sources[0x0d]	80863	1			T38	1		T41	4		T42	12
valid_sources[0x0e]	69092	1			T38	8		T41	2		T42	5
valid_sources[0x0f]	73439	1			T36	17		T37	1		T38	3
valid_sources[0x10]	72661	1			T37	1		T38	8		T41	1
valid_sources[0x11]	76499	1			T38	6		T42	6		T43	1
valid_sources[0x12]	74612	1			T37	1		T39	2		T41	1
valid_sources[0x13]	81567	1			T37	1		T38	5		T41	1
valid_sources[0x14]	73154	1			T38	1		T42	8		T43	2
valid_sources[0x15]	76140	1			T37	1		T38	8		T42	14
valid_sources[0x16]	69966	1			T37	3		T38	16		T41	2
valid_sources[0x17]	72877	1			T37	1		T38	11		T41	2
valid_sources[0x18]	75330	1			T37	3		T38	11		T41	1
valid_sources[0x19]	74241	1			T36	4		T37	1		T41	4
valid_sources[0x1a]	73400	1			T37	1		T38	3		T41	2
valid_sources[0x1b]	74872	1			T41	6		T42	13		T43	2
valid_sources[0x1c]	73703	1			T38	1		T39	14		T42	8
valid_sources[0x1d]	75176	1			T37	1		T38	2		T42	12
valid_sources[0x1e]	73678	1			T37	2		T39	6		T41	5
valid_sources[0x1f]	74294	1			T35	74		T37	1		T38	3
valid_sources[0x20]	79128	1			T42	6		T154	7		T75	15
valid_sources[0x21]	80605	1			T38	8		T43	1		T154	3
valid_sources[0x22]	71119	1			T38	2		T39	6		T41	4
valid_sources[0x23]	76839	1			T37	1		T38	2		T42	10
valid_sources[0x24]	74693	1			T37	1		T38	13		T39	5
valid_sources[0x25]	80983	1			T37	2		T42	13		T43	3
valid_sources[0x26]	74479	1			T37	1		T38	1		T42	10
valid_sources[0x27]	79170	1			T37	2		T38	5		T41	3
valid_sources[0x28]	79444	1			T41	1		T42	10		T43	5
valid_sources[0x29]	77885	1			T37	1		T43	5		T154	3
valid_sources[0x2a]	68469	1			T38	8		T41	2		T42	8
valid_sources[0x2b]	80320	1			T38	7		T41	4		T42	2
valid_sources[0x2c]	72994	1			T37	2		T39	2		T42	12
valid_sources[0x2d]	72911	1			T38	8		T39	15		T41	2
valid_sources[0x2e]	75154	1			T37	1		T38	8		T39	8
valid_sources[0x2f]	75772	1			T37	1		T38	4		T39	10
valid_sources[0x30]	79251	1			T37	2		T38	9		T41	2
valid_sources[0x31]	82216	1			T37	1		T38	6		T42	7
valid_sources[0x32]	72997	1			T41	3		T42	6		T43	2
valid_sources[0x33]	71155	1			T37	1		T41	1		T42	5
valid_sources[0x34]	74263	1			T38	2		T42	7		T43	1
valid_sources[0x35]	77167	1			T36	5		T37	2		T38	10
valid_sources[0x36]	72810	1			T37	1		T41	4		T42	12
valid_sources[0x37]	70939	1			T37	2		T38	4		T41	1
valid_sources[0x38]	212404	1			T38	2		T42	1		T43	1
valid_sources[0x39]	74708	1			T37	1		T38	3		T39	1
valid_sources[0x3a]	82129	1			T38	5		T41	4		T42	7
valid_sources[0x3b]	74690	1			T36	2		T37	2		T38	14
valid_sources[0x3c]	118398	1			T38	2		T39	3		T41	1
valid_sources[0x3d]	77087	1			T38	2		T41	4		T42	16
valid_sources[0x3e]	69373	1			T41	3		T42	11		T43	3
valid_sources[0x3f]	76868	1			T37	1		T38	19		T41	1
valid_sources[0x40]	75839	1			T37	1		T41	2		T42	4
valid_sources[0x41]	71083	1			T36	3		T38	1		T39	3
valid_sources[0x42]	72852	1			T37	3		T39	1		T41	2
valid_sources[0x43]	71772	1			T39	24		T41	1		T42	9
valid_sources[0x44]	73649	1			T37	3		T38	3		T39	3
valid_sources[0x45]	79403	1			T37	1		T38	19		T41	1
valid_sources[0x46]	81525	1			T37	1		T38	10		T41	4
valid_sources[0x47]	73837	1			T37	1		T38	4		T41	3
valid_sources[0x48]	71763	1			T36	5		T37	1		T38	5
valid_sources[0x49]	74351	1			T37	1		T38	1		T41	1
valid_sources[0x4a]	74744	1			T41	2		T42	12		T43	3
valid_sources[0x4b]	74276	1			T37	1		T38	16		T39	2
valid_sources[0x4c]	233394	1			T38	12		T39	5		T41	5
valid_sources[0x4d]	79801	1			T37	2		T41	1		T42	4
valid_sources[0x4e]	73074	1			T37	2		T38	17		T39	3
valid_sources[0x4f]	194231	1			T37	2		T41	1		T42	7
valid_sources[0x50]	71412	1			T38	3		T41	1		T42	5
valid_sources[0x51]	73699	1			T38	2		T39	2		T41	2
valid_sources[0x52]	75815	1			T37	1		T38	6		T41	1
valid_sources[0x53]	79361	1			T37	1		T38	5		T39	1
valid_sources[0x54]	82981	1			T38	11		T41	5		T42	12
valid_sources[0x55]	82939	1			T37	1		T38	5		T41	1
valid_sources[0x56]	77792	1			T38	2		T39	7		T41	1
valid_sources[0x57]	77419	1			T38	3		T41	7		T42	11
valid_sources[0x58]	73088	1			T37	1		T38	1		T39	8
valid_sources[0x59]	73798	1			T36	1		T39	3		T41	1
valid_sources[0x5a]	70098	1			T36	4		T38	7		T39	5
valid_sources[0x5b]	73196	1			T37	1		T41	7		T42	7
valid_sources[0x5c]	73494	1			T36	3		T38	9		T39	9
valid_sources[0x5d]	76052	1			T38	16		T41	3		T42	10
valid_sources[0x5e]	79949	1			T38	8		T41	4		T42	7
valid_sources[0x5f]	73185	1			T41	2		T42	7		T154	2
valid_sources[0x60]	78080	1			T37	3		T38	2		T39	1
valid_sources[0x61]	78746	1			T37	1		T41	3		T42	9
valid_sources[0x62]	126102	1			T37	1		T38	4		T41	2
valid_sources[0x63]	76591	1			T37	1		T41	1		T42	4
valid_sources[0x64]	80407	1			T37	1		T38	6		T39	6
valid_sources[0x65]	72960	1			T38	17		T42	6		T43	2
valid_sources[0x66]	81661	1			T37	1		T38	1		T42	14
valid_sources[0x67]	73311	1			T38	2		T39	6		T41	1
valid_sources[0x68]	79058	1			T36	1		T38	1		T41	2
valid_sources[0x69]	73767	1			T37	1		T38	7		T39	19
valid_sources[0x6a]	73401	1			T38	11		T41	1		T42	2
valid_sources[0x6b]	81588	1			T38	4		T42	12		T43	6
valid_sources[0x6c]	74842	1			T37	1		T38	6		T42	4
valid_sources[0x6d]	74664	1			T37	1		T38	5		T39	7
valid_sources[0x6e]	80757	1			T37	2		T38	4		T41	3
valid_sources[0x6f]	83989	1			T37	1		T42	5		T43	1
valid_sources[0x70]	76021	1			T37	3		T38	5		T41	1
valid_sources[0x71]	80043	1			T37	2		T38	9		T39	5
valid_sources[0x72]	75367	1			T37	2		T38	5		T41	4
valid_sources[0x73]	76433	1			T37	1		T38	4		T39	3
valid_sources[0x74]	74852	1			T37	1		T38	5		T41	3
valid_sources[0x75]	79918	1			T38	8		T41	1		T42	10
valid_sources[0x76]	77215	1			T37	2		T38	12		T39	13
valid_sources[0x77]	70740	1			T37	1		T38	2		T41	8
valid_sources[0x78]	77378	1			T37	1		T38	5		T41	2
valid_sources[0x79]	70175	1			T37	1		T42	8		T43	3
valid_sources[0x7a]	78337	1			T38	4		T41	7		T42	3
valid_sources[0x7b]	82390	1			T36	1		T38	1		T41	2
valid_sources[0x7c]	71011	1			T37	4		T39	7		T41	1
valid_sources[0x7d]	73510	1			T38	4		T39	4		T41	3
valid_sources[0x7e]	74204	1			T37	3		T38	5		T39	4
valid_sources[0x7f]	82591	1			T42	13		T43	4		T154	4
valid_sources[0x80]	77760	1			T37	2		T38	6		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4721604

1

T35

8

T36

9

T37

9

values[0x0]

all_enables

biggest_size

6079643

1

T35

34

T36

27

T37

127

values[0x1]

all_enables

biggest_size

6079640

1

T35

20

T36

19

T37

113