Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	174390764	0	0	0
ctrl_en_input_filter_rd_A	174390764	87433	0	0
intr_ctrl_en_falling_rd_A	174390764	90034	0	0
intr_ctrl_en_lvlhigh_rd_A	174390764	88096	0	0
intr_ctrl_en_lvllow_rd_A	174390764	89355	0	0
intr_ctrl_en_rising_rd_A	174390764	88500	0	0
intr_enable_rd_A	174390764	88373	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	87433	0	0
T1	15745	128	0	0
T2	174562	4235	0	0
T3	948857	2876	0	0
T4	0	183	0	0
T5	0	55	0	0
T6	0	227	0	0
T7	0	63	0	0
T8	0	1995	0	0
T9	0	96	0	0
T10	0	4424	0	0
T11	10613	0	0	0
T12	1196	0	0	0
T13	2874	0	0	0
T14	6003	0	0	0
T15	5838	0	0	0
T16	5563	0	0	0
T17	15331	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	90034	0	0
T1	0	140	0	0
T2	0	4475	0	0
T3	0	2938	0	0
T4	0	158	0	0
T5	0	56	0	0
T6	0	272	0	0
T7	0	69	0	0
T18	4799	9	0	0
T19	6806	8	0	0
T20	0	9	0	0
T21	2041	0	0	0
T22	4732	0	0	0
T23	2523	0	0	0
T24	7224	0	0	0
T25	88182	0	0	0
T26	3162	0	0	0
T27	5747	0	0	0
T28	9142	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	88096	0	0
T1	15745	133	0	0
T2	174562	4407	0	0
T3	948857	2715	0	0
T4	0	206	0	0
T5	0	72	0	0
T6	0	283	0	0
T7	0	98	0	0
T8	0	2151	0	0
T9	0	90	0	0
T10	0	4550	0	0
T11	10613	0	0	0
T12	1196	0	0	0
T13	2874	0	0	0
T14	6003	0	0	0
T15	5838	0	0	0
T16	5563	0	0	0
T17	15331	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	89355	0	0
T1	0	153	0	0
T2	0	4376	0	0
T3	0	3019	0	0
T4	0	175	0	0
T5	0	67	0	0
T6	0	251	0	0
T7	0	57	0	0
T8	0	2205	0	0
T18	4799	5	0	0
T19	6806	2	0	0
T21	2041	0	0	0
T22	4732	0	0	0
T23	2523	0	0	0
T24	7224	0	0	0
T25	88182	0	0	0
T26	3162	0	0	0
T27	5747	0	0	0
T28	9142	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	88500	0	0
T1	0	190	0	0
T2	0	4990	0	0
T3	0	3042	0	0
T4	0	201	0	0
T5	0	63	0	0
T6	0	270	0	0
T7	0	31	0	0
T18	4799	5	0	0
T19	6806	1	0	0
T21	2041	0	0	0
T22	4732	0	0	0
T23	2523	0	0	0
T24	7224	0	0	0
T25	88182	0	0	0
T26	3162	0	0	0
T27	5747	0	0	0
T28	9142	0	0	0
T29	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174390764	88373	0	0
T1	0	167	0	0
T2	0	4523	0	0
T3	0	3040	0	0
T4	0	198	0	0
T5	0	52	0	0
T6	0	255	0	0
T7	0	64	0	0
T8	0	2032	0	0
T19	6806	5	0	0
T25	88182	0	0	0
T26	3162	0	0	0
T27	5747	0	0	0
T28	9142	0	0	0
T29	0	2	0	0
T30	62078	0	0	0
T31	56154	0	0	0
T32	3407	0	0	0
T33	5897	0	0	0
T34	3677	0	0	0