Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	179100308	0	0	0
ctrl_en_input_filter_rd_A	179100308	57946	0	0
intr_ctrl_en_falling_rd_A	179100308	59198	0	0
intr_ctrl_en_lvlhigh_rd_A	179100308	57214	0	0
intr_ctrl_en_lvllow_rd_A	179100308	57552	0	0
intr_ctrl_en_rising_rd_A	179100308	57568	0	0
intr_enable_rd_A	179100308	57820	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	57946	0	0
T1	553336	1972	0	0
T2	0	193	0	0
T3	0	145	0	0
T4	0	9498	0	0
T5	0	361	0	0
T6	0	120	0	0
T7	0	332	0	0
T8	0	110	0	0
T9	0	69	0	0
T10	0	7267	0	0
T11	3918	0	0	0
T12	8151	0	0	0
T13	6244	0	0	0
T14	587716	0	0	0
T15	1977	0	0	0
T16	4383	0	0	0
T17	4186	0	0	0
T18	3785	0	0	0
T19	2463	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	59198	0	0
T1	553336	2020	0	0
T2	0	162	0	0
T3	0	128	0	0
T4	0	10173	0	0
T5	0	277	0	0
T6	0	101	0	0
T7	0	363	0	0
T8	0	87	0	0
T9	0	89	0	0
T10	0	7783	0	0
T11	3918	0	0	0
T12	8151	0	0	0
T13	6244	0	0	0
T14	587716	0	0	0
T15	1977	0	0	0
T16	4383	0	0	0
T17	4186	0	0	0
T18	3785	0	0	0
T19	2463	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	57214	0	0
T1	553336	1999	0	0
T2	0	207	0	0
T3	0	119	0	0
T4	0	9802	0	0
T5	0	282	0	0
T6	0	135	0	0
T7	0	259	0	0
T8	0	158	0	0
T9	0	48	0	0
T11	3918	0	0	0
T12	8151	0	0	0
T13	6244	0	0	0
T14	587716	0	0	0
T15	1977	0	0	0
T16	4383	0	0	0
T17	4186	0	0	0
T18	3785	0	0	0
T19	2463	0	0	0
T20	0	8	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	57552	0	0
T1	553336	2093	0	0
T2	0	240	0	0
T3	0	133	0	0
T4	0	9474	0	0
T5	0	317	0	0
T6	0	134	0	0
T7	0	349	0	0
T8	0	130	0	0
T11	3918	0	0	0
T12	8151	0	0	0
T13	6244	0	0	0
T14	587716	0	0	0
T15	1977	0	0	0
T16	4383	0	0	0
T20	0	4	0	0
T21	2627	4	0	0
T22	2207	0	0	0
T23	8327	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	57568	0	0
T1	553336	2004	0	0
T2	0	147	0	0
T3	0	122	0	0
T4	0	9443	0	0
T5	0	303	0	0
T6	0	115	0	0
T7	0	289	0	0
T8	0	98	0	0
T9	0	44	0	0
T10	0	7304	0	0
T11	3918	0	0	0
T12	8151	0	0	0
T13	6244	0	0	0
T14	587716	0	0	0
T15	1977	0	0	0
T16	4383	0	0	0
T17	4186	0	0	0
T18	3785	0	0	0
T19	2463	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179100308	57820	0	0
T1	553336	1919	0	0
T2	0	164	0	0
T3	0	106	0	0
T4	0	9587	0	0
T5	0	227	0	0
T6	0	112	0	0
T7	0	349	0	0
T8	0	114	0	0
T9	0	101	0	0
T10	0	7499	0	0
T11	3918	0	0	0
T12	8151	0	0	0
T13	6244	0	0	0
T14	587716	0	0	0
T15	1977	0	0	0
T16	4383	0	0	0
T17	4186	0	0	0
T18	3785	0	0	0
T19	2463	0	0	0