Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2652066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11034665

1

T22

183

T23

177

T24

544

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5652634	1			T22	112		T23	21		T24	666
values[0x0]	3963941	1			T22	65		T23	96		T24	106
values[0x1]	4070156	1			T22	62		T23	68		T24	116

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2061355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

11625376

1

T22

193

T23

179

T24

627

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54032	1			T23	2		T12	206		T14	10
valid_sources[0x01]	46912	1			T22	1		T25	3		T11	3
valid_sources[0x02]	50535	1			T22	1		T25	3		T11	1
valid_sources[0x03]	49796	1			T23	1		T25	2		T11	3
valid_sources[0x04]	50618	1			T25	3		T11	2		T12	180
valid_sources[0x05]	51803	1			T25	2		T11	2		T12	182
valid_sources[0x06]	50814	1			T22	1		T23	1		T25	4
valid_sources[0x07]	70280	1			T23	8		T25	4		T1	22467
valid_sources[0x08]	56027	1			T22	2		T25	1		T12	219
valid_sources[0x09]	49378	1			T23	1		T25	2		T11	3
valid_sources[0x0a]	50742	1			T22	3		T25	1		T12	187
valid_sources[0x0b]	55076	1			T23	1		T25	4		T11	2
valid_sources[0x0c]	47822	1			T22	2		T23	5		T25	2
valid_sources[0x0d]	48836	1			T25	4		T12	177		T14	12
valid_sources[0x0e]	60299	1			T22	1		T25	1		T11	2
valid_sources[0x0f]	53541	1			T22	2		T23	8		T25	1
valid_sources[0x10]	48355	1			T22	1		T25	2		T11	1
valid_sources[0x11]	48465	1			T25	3		T11	4		T12	203
valid_sources[0x12]	57674	1			T23	1		T25	1		T11	1
valid_sources[0x13]	54271	1			T25	1		T11	1		T12	174
valid_sources[0x14]	47967	1			T22	2		T23	1		T25	7
valid_sources[0x15]	56427	1			T22	2		T25	3		T11	3
valid_sources[0x16]	64840	1			T25	2		T11	2		T12	227
valid_sources[0x17]	48546	1			T23	1		T25	2		T12	214
valid_sources[0x18]	52057	1			T23	4		T25	1		T12	198
valid_sources[0x19]	54428	1			T25	3		T11	1		T12	172
valid_sources[0x1a]	48799	1			T25	1		T11	2		T12	190
valid_sources[0x1b]	53840	1			T11	2		T12	220		T14	12
valid_sources[0x1c]	51398	1			T25	2		T11	1		T12	249
valid_sources[0x1d]	56776	1			T25	1		T11	1		T12	200
valid_sources[0x1e]	51108	1			T25	6		T12	191		T13	4
valid_sources[0x1f]	51578	1			T22	1		T25	5		T11	1
valid_sources[0x20]	47363	1			T22	3		T25	5		T12	245
valid_sources[0x21]	51765	1			T25	6		T11	2		T12	200
valid_sources[0x22]	51182	1			T22	1		T25	4		T11	1
valid_sources[0x23]	52720	1			T25	2		T12	190		T14	12
valid_sources[0x24]	48469	1			T22	1		T23	1		T25	3
valid_sources[0x25]	50811	1			T22	1		T25	3		T11	2
valid_sources[0x26]	53692	1			T22	1		T23	1		T25	4
valid_sources[0x27]	55541	1			T22	5		T23	1		T25	7
valid_sources[0x28]	56035	1			T22	4		T25	4		T12	239
valid_sources[0x29]	51021	1			T23	4		T25	2		T11	1
valid_sources[0x2a]	53794	1			T25	5		T11	3		T12	241
valid_sources[0x2b]	49958	1			T22	2		T25	3		T12	247
valid_sources[0x2c]	50768	1			T23	1		T25	2		T11	3
valid_sources[0x2d]	46718	1			T23	1		T25	1		T12	215
valid_sources[0x2e]	47315	1			T25	7		T11	1		T12	216
valid_sources[0x2f]	50446	1			T25	2		T11	1		T12	222
valid_sources[0x30]	47273	1			T25	2		T11	1		T12	194
valid_sources[0x31]	49639	1			T22	3		T23	6		T25	3
valid_sources[0x32]	51243	1			T22	2		T23	1		T25	4
valid_sources[0x33]	53501	1			T22	1		T25	2		T11	2
valid_sources[0x34]	191037	1			T22	3		T25	2		T11	2
valid_sources[0x35]	47437	1			T22	3		T25	3		T11	1
valid_sources[0x36]	47589	1			T25	2		T11	4		T12	208
valid_sources[0x37]	50462	1			T22	1		T25	5		T12	183
valid_sources[0x38]	53169	1			T22	1		T23	2		T25	3
valid_sources[0x39]	51248	1			T25	4		T11	5		T12	238
valid_sources[0x3a]	52625	1			T22	3		T25	1		T11	2
valid_sources[0x3b]	51196	1			T22	1		T23	2		T25	3
valid_sources[0x3c]	57118	1			T22	1		T25	2		T11	2
valid_sources[0x3d]	55108	1			T22	2		T23	2		T25	1
valid_sources[0x3e]	49663	1			T22	1		T25	1		T11	2
valid_sources[0x3f]	55923	1			T25	1		T11	1		T12	224
valid_sources[0x40]	50452	1			T22	1		T25	4		T11	4
valid_sources[0x41]	47006	1			T23	1		T25	3		T12	148
valid_sources[0x42]	49807	1			T22	1		T25	5		T11	1
valid_sources[0x43]	49475	1			T22	2		T25	3		T11	1
valid_sources[0x44]	56261	1			T22	1		T25	4		T12	193
valid_sources[0x45]	53180	1			T22	1		T25	3		T12	232
valid_sources[0x46]	54226	1			T23	1		T25	4		T11	2
valid_sources[0x47]	51593	1			T22	2		T23	2		T25	1
valid_sources[0x48]	50492	1			T25	3		T12	217		T13	2
valid_sources[0x49]	48721	1			T22	1		T23	3		T25	3
valid_sources[0x4a]	48142	1			T22	3		T25	4		T11	1
valid_sources[0x4b]	49296	1			T22	4		T25	3		T11	1
valid_sources[0x4c]	50368	1			T25	3		T11	3		T12	216
valid_sources[0x4d]	48649	1			T22	4		T25	2		T11	2
valid_sources[0x4e]	51108	1			T22	1		T23	3		T25	4
valid_sources[0x4f]	51715	1			T23	2		T25	2		T11	5
valid_sources[0x50]	48610	1			T22	1		T23	1		T25	5
valid_sources[0x51]	53655	1			T22	1		T25	4		T11	1
valid_sources[0x52]	51712	1			T25	2		T11	4		T12	222
valid_sources[0x53]	53437	1			T25	6		T11	1		T12	215
valid_sources[0x54]	57770	1			T25	2		T11	2		T12	172
valid_sources[0x55]	46611	1			T25	2		T11	1		T12	232
valid_sources[0x56]	47401	1			T25	3		T11	1		T12	218
valid_sources[0x57]	52150	1			T22	4		T25	2		T11	1
valid_sources[0x58]	52914	1			T22	2		T11	1		T12	237
valid_sources[0x59]	53069	1			T22	1		T25	5		T11	6
valid_sources[0x5a]	46956	1			T23	4		T25	5		T11	4
valid_sources[0x5b]	52836	1			T22	1		T25	1		T11	3
valid_sources[0x5c]	48718	1			T23	4		T25	4		T12	254
valid_sources[0x5d]	46548	1			T22	1		T25	3		T11	2
valid_sources[0x5e]	50783	1			T22	2		T25	3		T11	1
valid_sources[0x5f]	49734	1			T23	3		T25	1		T11	1
valid_sources[0x60]	50022	1			T22	3		T11	2		T12	174
valid_sources[0x61]	46553	1			T22	1		T25	2		T12	212
valid_sources[0x62]	50797	1			T25	2		T12	239		T13	1
valid_sources[0x63]	152456	1			T22	2		T23	1		T25	3
valid_sources[0x64]	52454	1			T23	2		T25	2		T11	2
valid_sources[0x65]	52258	1			T23	2		T25	3		T11	2
valid_sources[0x66]	53492	1			T11	1		T12	249		T13	1
valid_sources[0x67]	51107	1			T25	2		T11	3		T12	259
valid_sources[0x68]	49187	1			T23	1		T25	2		T11	1
valid_sources[0x69]	50796	1			T22	1		T23	1		T25	7
valid_sources[0x6a]	53585	1			T25	6		T12	220		T14	22
valid_sources[0x6b]	53749	1			T23	3		T25	2		T11	1
valid_sources[0x6c]	53285	1			T22	1		T23	1		T25	2
valid_sources[0x6d]	48609	1			T25	1		T11	2		T12	189
valid_sources[0x6e]	48289	1			T25	2		T11	2		T12	200
valid_sources[0x6f]	48431	1			T25	4		T11	3		T12	207
valid_sources[0x70]	50731	1			T22	2		T23	2		T25	5
valid_sources[0x71]	52037	1			T25	3		T11	3		T12	224
valid_sources[0x72]	49332	1			T25	3		T11	1		T12	173
valid_sources[0x73]	53632	1			T23	1		T25	4		T12	174
valid_sources[0x74]	53184	1			T25	2		T11	1		T12	222
valid_sources[0x75]	53013	1			T22	3		T23	2		T25	3
valid_sources[0x76]	48297	1			T22	3		T23	4		T25	4
valid_sources[0x77]	54585	1			T22	3		T23	3		T25	1
valid_sources[0x78]	48293	1			T22	2		T23	1		T25	3
valid_sources[0x79]	52166	1			T22	1		T25	3		T11	1
valid_sources[0x7a]	48097	1			T25	3		T12	214		T14	14
valid_sources[0x7b]	56923	1			T23	2		T25	3		T11	1
valid_sources[0x7c]	48376	1			T23	1		T25	2		T12	173
valid_sources[0x7d]	50368	1			T25	2		T11	3		T12	207
valid_sources[0x7e]	54781	1			T22	1		T25	3		T11	1
valid_sources[0x7f]	52855	1			T23	2		T25	3		T11	1
valid_sources[0x80]	50848	1			T25	2		T12	228		T13	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3130267

1

T22

56

T23

13

T24

322

values[0x0]

all_enables

biggest_size

3952785

1

T22

65

T23

96

T24

106

values[0x1]

all_enables

biggest_size

3951613

1

T22

62

T23

68

T24

116