Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105586852	0	0	0
ctrl_en_input_filter_rd_A	105586852	51804	0	0
intr_ctrl_en_falling_rd_A	105586852	52492	0	0
intr_ctrl_en_lvlhigh_rd_A	105586852	51508	0	0
intr_ctrl_en_lvllow_rd_A	105586852	51948	0	0
intr_ctrl_en_rising_rd_A	105586852	52205	0	0
intr_enable_rd_A	105586852	53304	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	51804	0	0
T1	321365	562	0	0
T2	35297	118	0	0
T3	0	1522	0	0
T4	0	1821	0	0
T5	0	97	0	0
T6	0	7	0	0
T7	0	3102	0	0
T8	0	5567	0	0
T9	0	2628	0	0
T10	0	120	0	0
T11	6064	0	0	0
T12	259121	0	0	0
T13	7381	0	0	0
T14	64483	0	0	0
T15	3080	0	0	0
T16	3813	0	0	0
T17	12460	0	0	0
T18	667185	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	52492	0	0
T1	321365	798	0	0
T2	35297	212	0	0
T3	0	1680	0	0
T4	0	1785	0	0
T5	0	65	0	0
T7	0	2773	0	0
T8	0	5438	0	0
T9	0	2612	0	0
T10	0	142	0	0
T11	6064	0	0	0
T12	259121	0	0	0
T13	7381	0	0	0
T14	64483	0	0	0
T15	3080	0	0	0
T16	3813	0	0	0
T17	12460	0	0	0
T18	667185	0	0	0
T19	0	3597	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	51508	0	0
T1	321365	775	0	0
T2	35297	172	0	0
T3	0	1723	0	0
T4	0	1882	0	0
T5	0	54	0	0
T6	0	7	0	0
T7	0	2783	0	0
T8	0	5417	0	0
T9	0	2724	0	0
T10	0	122	0	0
T11	6064	0	0	0
T12	259121	0	0	0
T13	7381	0	0	0
T14	64483	0	0	0
T15	3080	0	0	0
T16	3813	0	0	0
T17	12460	0	0	0
T18	667185	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	51948	0	0
T1	321365	746	0	0
T2	35297	92	0	0
T3	0	1460	0	0
T4	0	1624	0	0
T5	0	68	0	0
T6	0	8	0	0
T7	0	2871	0	0
T8	0	5271	0	0
T9	0	2816	0	0
T11	6064	0	0	0
T12	259121	0	0	0
T13	7381	0	0	0
T14	64483	0	0	0
T15	3080	0	0	0
T16	3813	0	0	0
T17	12460	0	0	0
T18	667185	0	0	0
T20	0	3	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	52205	0	0
T1	321365	788	0	0
T2	35297	140	0	0
T3	0	1555	0	0
T4	0	1676	0	0
T5	0	47	0	0
T7	0	2835	0	0
T8	0	5867	0	0
T9	0	2831	0	0
T11	6064	0	0	0
T12	259121	0	0	0
T13	7381	0	0	0
T14	64483	0	0	0
T15	3080	0	0	0
T16	3813	0	0	0
T17	12460	0	0	0
T18	667185	0	0	0
T20	0	5	0	0
T21	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105586852	53304	0	0
T1	321365	734	0	0
T2	35297	86	0	0
T3	0	1551	0	0
T4	0	2105	0	0
T5	0	65	0	0
T6	0	15	0	0
T7	0	3131	0	0
T8	0	5702	0	0
T9	0	2652	0	0
T11	6064	0	0	0
T12	259121	0	0	0
T13	7381	0	0	0
T14	64483	0	0	0
T15	3080	0	0	0
T16	3813	0	0	0
T17	12460	0	0	0
T18	667185	0	0	0
T21	0	1	0	0