Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_gpio_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4703845	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

21161416

1

T32

460801

T33

769

T34

1712

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10306405	1			T32	211174		T33	1192		T34	795
values[0x0]	7643007	1			T32	167481		T33	76		T34	683
values[0x1]	7915849	1			T32	175180		T33	82		T34	638

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3610639	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

22254622

1

T32

483690

T33

890

T34

1794

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	90944	1			T32	2136		T34	13		T39	4
valid_sources[0x01]	94074	1			T32	2065		T33	1		T34	4
valid_sources[0x02]	97373	1			T32	2097		T34	4		T39	10
valid_sources[0x03]	93504	1			T32	2180		T33	47		T34	5
valid_sources[0x04]	103629	1			T32	2100		T34	12		T38	1
valid_sources[0x05]	100041	1			T32	2179		T34	5		T39	18
valid_sources[0x06]	96364	1			T32	2150		T34	5		T37	344
valid_sources[0x07]	95881	1			T32	2182		T33	32		T34	8
valid_sources[0x08]	89217	1			T32	2160		T33	12		T34	6
valid_sources[0x09]	88286	1			T32	2226		T33	12		T34	10
valid_sources[0x0a]	90266	1			T32	2105		T34	11		T38	2
valid_sources[0x0b]	99731	1			T32	2167		T34	7		T39	9
valid_sources[0x0c]	92850	1			T32	2191		T33	3		T34	5
valid_sources[0x0d]	94343	1			T32	2241		T34	4		T38	1
valid_sources[0x0e]	94295	1			T32	2136		T34	6		T39	9
valid_sources[0x0f]	98937	1			T32	2176		T34	6		T38	1
valid_sources[0x10]	171459	1			T32	2174		T33	5		T34	7
valid_sources[0x11]	94557	1			T32	2157		T34	17		T38	1
valid_sources[0x12]	93366	1			T32	2194		T33	6		T34	6
valid_sources[0x13]	92199	1			T32	2242		T33	13		T34	7
valid_sources[0x14]	91931	1			T32	2098		T33	13		T34	6
valid_sources[0x15]	93321	1			T32	2230		T34	9		T39	3
valid_sources[0x16]	91291	1			T32	2151		T33	1		T34	12
valid_sources[0x17]	172654	1			T32	2249		T34	5		T39	6
valid_sources[0x18]	89125	1			T32	2138		T33	4		T34	8
valid_sources[0x19]	95308	1			T32	2125		T33	17		T34	5
valid_sources[0x1a]	93627	1			T32	2138		T33	9		T34	2
valid_sources[0x1b]	87130	1			T32	2212		T34	9		T38	1
valid_sources[0x1c]	250406	1			T32	2247		T33	32		T34	8
valid_sources[0x1d]	84602	1			T32	2084		T34	8		T39	11
valid_sources[0x1e]	107008	1			T32	2217		T34	12		T38	1
valid_sources[0x1f]	87093	1			T32	2145		T33	2		T34	8
valid_sources[0x20]	105580	1			T32	2075		T33	15		T34	6
valid_sources[0x21]	103134	1			T32	2157		T33	19		T34	9
valid_sources[0x22]	99225	1			T32	2092		T34	7		T39	10
valid_sources[0x23]	90114	1			T32	2224		T34	6		T39	4
valid_sources[0x24]	97919	1			T32	2142		T33	4		T34	10
valid_sources[0x25]	94970	1			T32	2188		T33	5		T34	4
valid_sources[0x26]	93131	1			T32	2191		T34	5		T38	1
valid_sources[0x27]	98662	1			T32	2146		T33	33		T34	5
valid_sources[0x28]	98097	1			T32	2198		T33	12		T34	13
valid_sources[0x29]	93301	1			T32	2163		T33	1		T34	6
valid_sources[0x2a]	96469	1			T32	2151		T33	2		T34	10
valid_sources[0x2b]	242180	1			T32	2092		T34	9		T36	82
valid_sources[0x2c]	93005	1			T32	2128		T34	8		T38	2
valid_sources[0x2d]	89900	1			T32	2203		T34	7		T39	6
valid_sources[0x2e]	93413	1			T32	2180		T34	16		T39	1
valid_sources[0x2f]	88905	1			T32	2164		T34	13		T38	1
valid_sources[0x30]	95747	1			T32	2116		T33	11		T34	3
valid_sources[0x31]	90334	1			T32	2208		T33	5		T34	4
valid_sources[0x32]	86292	1			T32	2189		T34	9		T39	15
valid_sources[0x33]	92480	1			T32	2195		T33	24		T34	7
valid_sources[0x34]	92049	1			T32	2176		T33	2		T34	2
valid_sources[0x35]	91897	1			T32	2144		T34	4		T39	5
valid_sources[0x36]	106306	1			T32	2174		T34	6		T38	2
valid_sources[0x37]	99682	1			T32	2167		T33	3		T34	3
valid_sources[0x38]	100666	1			T32	2160		T33	18		T34	7
valid_sources[0x39]	93101	1			T32	2210		T33	14		T34	9
valid_sources[0x3a]	89608	1			T32	2177		T34	10		T38	1
valid_sources[0x3b]	89984	1			T32	2182		T34	5		T36	24
valid_sources[0x3c]	96418	1			T32	2152		T34	5		T38	2
valid_sources[0x3d]	187714	1			T32	2227		T33	1		T34	10
valid_sources[0x3e]	108662	1			T32	2148		T33	13		T34	11
valid_sources[0x3f]	94378	1			T32	2223		T34	4		T38	1
valid_sources[0x40]	85022	1			T32	2062		T34	11		T39	3
valid_sources[0x41]	88006	1			T32	2181		T34	9		T38	2
valid_sources[0x42]	105161	1			T32	2253		T33	8		T34	6
valid_sources[0x43]	242021	1			T32	2166		T34	14		T39	1
valid_sources[0x44]	91140	1			T32	2178		T34	6		T38	2
valid_sources[0x45]	89985	1			T32	2202		T34	4		T39	6
valid_sources[0x46]	91089	1			T32	2286		T33	3		T34	9
valid_sources[0x47]	92814	1			T32	2137		T33	11		T34	7
valid_sources[0x48]	147177	1			T32	2063		T33	7		T34	10
valid_sources[0x49]	99102	1			T32	2148		T34	13		T38	1
valid_sources[0x4a]	89691	1			T32	2166		T34	8		T39	15
valid_sources[0x4b]	121882	1			T32	2121		T33	4		T34	8
valid_sources[0x4c]	93924	1			T32	2258		T34	13		T38	1
valid_sources[0x4d]	94202	1			T32	2201		T34	15		T39	4
valid_sources[0x4e]	104166	1			T32	2116		T33	1		T34	11
valid_sources[0x4f]	86658	1			T32	2122		T33	19		T34	7
valid_sources[0x50]	93360	1			T32	2168		T34	11		T39	6
valid_sources[0x51]	173649	1			T32	2138		T34	11		T36	46
valid_sources[0x52]	97165	1			T32	2293		T34	13		T38	1
valid_sources[0x53]	93634	1			T32	2143		T33	9		T34	12
valid_sources[0x54]	95226	1			T32	2207		T33	3		T34	13
valid_sources[0x55]	92731	1			T32	2113		T33	11		T34	8
valid_sources[0x56]	92002	1			T32	2153		T33	22		T34	11
valid_sources[0x57]	95888	1			T32	2205		T34	6		T38	3
valid_sources[0x58]	126508	1			T32	2181		T34	21		T39	1
valid_sources[0x59]	96118	1			T32	2154		T34	7		T38	2
valid_sources[0x5a]	98842	1			T32	2174		T33	12		T34	12
valid_sources[0x5b]	93335	1			T32	2201		T34	7		T39	6
valid_sources[0x5c]	94173	1			T32	2285		T33	1		T34	8
valid_sources[0x5d]	95808	1			T32	2176		T34	7		T38	1
valid_sources[0x5e]	91251	1			T32	2154		T34	4		T38	2
valid_sources[0x5f]	96997	1			T32	2105		T34	6		T38	1
valid_sources[0x60]	88768	1			T32	2219		T34	5		T38	1
valid_sources[0x61]	103726	1			T32	2172		T33	1		T34	5
valid_sources[0x62]	92838	1			T32	2149		T33	4		T34	5
valid_sources[0x63]	97938	1			T32	2152		T33	6		T34	4
valid_sources[0x64]	91697	1			T32	2145		T34	3		T38	1
valid_sources[0x65]	88037	1			T32	2170		T33	41		T34	8
valid_sources[0x66]	109777	1			T32	2075		T34	8		T38	1
valid_sources[0x67]	94982	1			T32	2166		T34	13		T36	62
valid_sources[0x68]	92433	1			T32	2223		T34	7		T39	8
valid_sources[0x69]	89571	1			T32	2136		T33	15		T34	14
valid_sources[0x6a]	90913	1			T32	2164		T33	20		T34	11
valid_sources[0x6b]	94791	1			T32	2137		T33	8		T34	10
valid_sources[0x6c]	89255	1			T32	2138		T33	8		T34	9
valid_sources[0x6d]	96017	1			T32	2148		T33	7		T34	9
valid_sources[0x6e]	87787	1			T32	2122		T33	13		T34	5
valid_sources[0x6f]	92180	1			T32	2195		T33	7		T34	14
valid_sources[0x70]	95273	1			T32	2111		T33	3		T34	7
valid_sources[0x71]	103711	1			T32	2212		T34	15		T38	1
valid_sources[0x72]	94385	1			T32	2075		T34	4		T39	3
valid_sources[0x73]	93939	1			T32	2215		T33	6		T34	8
valid_sources[0x74]	94223	1			T32	2126		T34	8		T38	1
valid_sources[0x75]	93468	1			T32	2170		T34	11		T38	1
valid_sources[0x76]	104227	1			T32	1992		T34	12		T39	9
valid_sources[0x77]	93506	1			T32	2138		T34	8		T39	8
valid_sources[0x78]	94799	1			T32	2177		T34	7		T38	1
valid_sources[0x79]	93283	1			T32	2120		T34	6		T38	1
valid_sources[0x7a]	181303	1			T32	2162		T33	34		T34	4
valid_sources[0x7b]	91642	1			T32	2098		T34	8		T39	4
valid_sources[0x7c]	88117	1			T32	2141		T33	15		T34	1
valid_sources[0x7d]	89575	1			T32	2142		T34	7		T39	5
valid_sources[0x7e]	94537	1			T32	2246		T34	9		T38	2
valid_sources[0x7f]	95289	1			T32	2099		T33	7		T34	11
valid_sources[0x80]	97876	1			T32	2276		T33	22		T34	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5927858

1

T32

127087

T33

611

T34

391

values[0x0]

all_enables

biggest_size

7615989

1

T32

166772

T33

76

T34

683

values[0x1]

all_enables

biggest_size

7617569

1

T32

166942

T33

82

T34

638