Unified Coverage Report :: Module :: gpio_csr_assert_fpv

Module : gpio_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_gpio_csr_assert_0/gpio_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gpio_csr_assert	85.71						85.71

---

Module Instance : tb.dut.gpio_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71						85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : gpio_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	6	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	6	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	192341863	0	0	0
ctrl_en_input_filter_rd_A	192341863	48786	0	0
intr_ctrl_en_falling_rd_A	192341863	48935	0	0
intr_ctrl_en_lvlhigh_rd_A	192341863	48529	0	0
intr_ctrl_en_lvllow_rd_A	192341863	48877	0	0
intr_ctrl_en_rising_rd_A	192341863	48806	0	0
intr_enable_rd_A	192341863	49346	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	0	0	0

ctrl_en_input_filter_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	48786	0	0
T1	5869	2	0	0
T2	0	2927	0	0
T3	0	251	0	0
T4	0	146	0	0
T5	0	34	0	0
T6	0	14	0	0
T7	0	411	0	0
T8	0	2783	0	0
T9	0	613	0	0
T10	0	174	0	0
T11	1320	0	0	0
T12	1933	0	0	0
T13	8172	0	0	0
T14	5465	0	0	0
T15	4780	0	0	0
T16	894	0	0	0
T17	6284	0	0	0
T18	966	0	0	0
T19	2881	0	0	0

intr_ctrl_en_falling_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	48935	0	0
T1	5869	3	0	0
T2	0	3020	0	0
T3	0	269	0	0
T4	0	281	0	0
T5	0	30	0	0
T6	0	4	0	0
T7	0	485	0	0
T8	0	3059	0	0
T9	0	703	0	0
T10	0	154	0	0
T11	1320	0	0	0
T12	1933	0	0	0
T13	8172	0	0	0
T14	5465	0	0	0
T15	4780	0	0	0
T16	894	0	0	0
T17	6284	0	0	0
T18	966	0	0	0
T19	2881	0	0	0

intr_ctrl_en_lvlhigh_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	48529	0	0
T1	5869	5	0	0
T2	0	2871	0	0
T3	0	209	0	0
T4	0	179	0	0
T5	0	27	0	0
T6	0	16	0	0
T7	0	482	0	0
T8	0	3136	0	0
T9	0	804	0	0
T10	0	154	0	0
T11	1320	0	0	0
T12	1933	0	0	0
T13	8172	0	0	0
T14	5465	0	0	0
T15	4780	0	0	0
T16	894	0	0	0
T17	6284	0	0	0
T18	966	0	0	0
T19	2881	0	0	0

intr_ctrl_en_lvllow_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	48877	0	0
T2	687857	2964	0	0
T3	0	236	0	0
T4	0	156	0	0
T5	0	57	0	0
T7	0	414	0	0
T8	0	3191	0	0
T9	0	748	0	0
T10	0	104	0	0
T20	0	1	0	0
T21	0	192	0	0
T22	15116	0	0	0
T23	4645	0	0	0
T24	14034	0	0	0
T25	3720	0	0	0
T26	2886	0	0	0
T27	2026	0	0	0
T28	75939	0	0	0
T29	139465	0	0	0
T30	7783	0	0	0

intr_ctrl_en_rising_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	48806	0	0
T2	687857	2872	0	0
T3	0	214	0	0
T4	0	178	0	0
T5	0	30	0	0
T6	0	9	0	0
T7	0	480	0	0
T8	0	3007	0	0
T9	0	718	0	0
T10	0	143	0	0
T21	0	213	0	0
T22	15116	0	0	0
T23	4645	0	0	0
T24	14034	0	0	0
T25	3720	0	0	0
T26	2886	0	0	0
T27	2026	0	0	0
T28	75939	0	0	0
T29	139465	0	0	0
T30	7783	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192341863	49346	0	0
T2	687857	2740	0	0
T3	0	168	0	0
T4	0	184	0	0
T5	0	48	0	0
T6	0	12	0	0
T7	0	417	0	0
T8	0	3127	0	0
T9	0	817	0	0
T20	0	1	0	0
T22	15116	0	0	0
T23	4645	0	0	0
T24	14034	0	0	0
T25	3720	0	0	0
T26	2886	0	0	0
T27	2026	0	0	0
T28	75939	0	0	0
T29	139465	0	0	0
T30	7783	0	0	0
T31	0	2	0	0